An energy and area efficient 4:2 compressor based on FinFETs
Introduction
In recent decades, exponential growth of integration of multimedia-based applications into portable electronic devices has taken place in the semiconductor industry. Subsequently, it has become significant to achieve the target of challenging criteria of emerging low-power and high-performance digital signal processing chips. In such battery-powered portable devices, digital signal processing blocks, as the most important parts of the system, operate with a limited amount of energy storage. On the other hand, the performance of these devices, is a critical issue due to variety of human interaction applications [1], [2].
Multiplier is one of the foremost arithmetic blocks in the commonly used microprocessor circuits. Especially, digital signal processing (DSP) relies on the efficient implementation of multipliers to execute dedicated algorithms such as filtering or convolution. Multiplier, as a significant and obligatory arithmetic component in digital signal processors, is the most time and energy consuming block for a vast range of applications, and consequently enhancing the performance and energy-efficiency of multipliers is quite important [3], [4].
A multiplier is conventionally composed of three stages including partial product generator, partial product reduction stage for reducing the partial products to only two operands in a carry-free structure, and a fast addition block for computing the final result [3]. Unlike the partial product generation, which is usually a constant time operation, the latencies of the partial product reduction and carry propagating addition steps have a logarithmic order with respect to the size of their inputs operands. However, among these blocks, the second stage occupies a large silicon area, contributes to the maximum propagation delay, and consumes a large amount of power, as compared to the other blocks. As a result, speeding up the carry save structure and lowering the power consumption in the partial product reduction block are desirable. The partial product reduction techniques such as Wallace and Dadda methods suffer from VLSI irregularity because of using only full adders [4], [5]. In order to enhance circuit regularity and reduce the latency and energy consumption of the partial product reduction stage, compressors can be utilized instead of full adders. Among different compressor structures, the 4:2 type is more preferred due to lower complexity as well as acceptable regularization [6].
During the last decades, technology scaling has facilitated performance improvement and energy reduction. Some important issues, such as severe short channel effects, high leakage power dissipation, and increased power density have become more challenging in nanoscale CMOS technologies [7]. FinFET has shown a wonderful scalability, due to suppression of short channel effects and smaller parametric variations. FinFET as an alternative to conventional bulk MOSFET, exhibits smaller drain induced barrier lowering (DIBL), smaller subthreshold swing and higher Ion/Ioff ratio by increasing electrostatic stability and reducing threshold voltage (VT) roll-off. In addition, FinFET eliminates the random dopant fluctuation (RDF), as a critical source of variation in nanometer CMOS technologies, due to its undoped body and superior gate control [8], [9].
In this paper, an energy and area efficient 4:2 compressor based on FinFETs for high-performance nanoscale arithmetic units is proposed. In this design, transistor-level innovations lead to reduction of the number of transistors and energy consumption.
In the remainder of this paper, in Section 2, the important existing 4:2 compressors are reviewed. In Section 3, the proposed design is introduced and described. Section 4 presents the simulation results and comparisons and finally, Section 5 concludes the paper.
Section snippets
Previous works
The schematic of a 4:2 compressor and its conventional implementation are illustrated in Fig. 1. This circuit has five input signals, including four main inputs and an input carry bit (Cin), coming from the previous stage, and three output signals including Sum and Carry main outputs and an output carry signal (Cout) which serves as the Cin of the next neighboring block. It is worth mentioning that the Cout signal is independent of the Cin input due to the elimination of carry propagation
Proposed design
In order to design a new arithmetic circuit, various methods can be exploited. Extracting a new arrangement of logic equations and making an innovation based on the truth table can lead to an efficient design. The novelty of the proposed approach for designing a new optimal 4:2 compressor is originated from a different sight into the truth table. Based on Table 2, the initiative step of the proposed design is the rewriting of the logic equations of the Sum, Carry outputs based on the input, ×1.
Simulation results and comparisons
In this section, the performance metrics of the proposed compressor are evaluated in different aspects and are compared with the related state-of-the-art designs in the literature. Simulations are performed using Synopsys HSPICE with the BSIM-CMG FinFET model [14] at room temperature, 2 GHz frequency and different supply voltages. Some of the important parameters of this model are given in Table 3.
All of the previous compressors are redesigned and optimized for energy-efficiency using FinFETs
Conclusion
In this study an energy and area efficient 4:2 compressor was proposed, based on a new logical structure. Reducing the area and enhancing the energy-efficiency were the main purposes for designing the proposed compressor. The proposed design has considerably lower number of transistors, smaller area and considerably higher energy-efficiency in comparison with previous designs, where it was designed and optimized based on tri-gate FinFETs. The simulation results indicated that the proposed
References (18)
- et al.
Comparative analysis of adiabatic full adder cells in CNFET technology
Eng. Sci. Technol. Int. J.
(2016) - et al.
Improved CMOS (4;2) compressor designs for parallel multipliers
Comput. Electr. Eng.
(2012) Ultra Low-Power Electronics and Design
(2004)- et al.
Digital Arithmetic
(2004) - D. Baran, M. Aktan, VojinG. Oklobdzija, Energy efficient implementation of parallel CMOS multipliers with improved...
- et al.
High-performance CMOS (4:2) compressors
Int. J. Electron.
(2014) - et al.
Analysis of crosstalk effects for multiwalled carbon nanotube bundle interconnects in ternary logic and comparison with Cu interconnects
IEEE Trans. Nanotechnol.
(2017) - et al.
Dual-Vth independent-gate FinFETs for low power logic circuits
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
(2011) - et al.
Low power robust FinFET-based SRAM design in scaled technologies
Circuit Des. Reliab.
(2015)
Cited by (49)
Improving the accuracy of approximate multipliers based on the characteristics of 4:2 compressors
2023, Microprocessors and MicrosystemsA Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits
2024, ACM Transactions on Design Automation of Electronic SystemsA fast and energy-efficient hybrid 4–2 compressor for multiplication in nanotechnology
2024, Journal of SupercomputingArea, power efficient Vedic multiplier architecture using novel 4:2 compressor
2023, Sadhana - Academy Proceedings in Engineering SciencesOn the Use of Low-power Devices, Approximate Adders and Near-threshold Operation for Energy-efficient Multipliers
2023, Journal of Integrated Circuits and Systems