A low-area, 43.5% PAE, 0.9 W, Class-E differential power amplifier in 2.4 GHz for IoT applications

Abstract

In this study, a new Class-E power amplifier (CEPA) with high efficiency, gain and output power for the Internet of things (IoT) applications is presented. Using cross coupling neutralization and fully differential topology in Class-E power amplifier, led to high-power efficiency, high-power gain and better reverses isolation. Cross coupled pair structure and the tuning LC tank oscillator are employed to decrease THD and power consumption. On the other hand, cross coupled capacitor could improve the performance of our design; and differential topology could cause high power efficiency, while cross coupled neutralization could increase PAE and power gain. The main contribution of this structure is employing cross capacitor intelligently. In this way, the capacitor used is not only contributing in stability enhancement, but also in die size diminishing. The performance and frequency range of the presented PA has appropriated it for IoT applications. The proposed Class-E amplifier can attain 29.5 dbm output power at 2.4 GHz with 43.5% and 36 dB of PAE and power gain, respectively. Furthermore, the proposed power amplifier can deliver 0.9 W to load. These results are verified by post layout simulations of the proposed PA performed by 0.18 µm standard CMOS technology.

Introduction

Currently, cybernetic-aspect applications and cyber-physical system are developed extremely. Cybernetic is defined as “the science of communication and control in animal or HUMAN and MACHINE” [1]. On the contrary, cyber-physical systems such as smart grid [2] and distributed robotics [3] are expanding rapidly.

IoT is one of the important practical issues in academic research that is made up of a number of different components. Transceiver is a major component in IoT devices which contains a number of blocks, including LNA, ADC, mixer, power amplifier etc. Power amplifiers are critical in RF transceivers because of high power consumption. On the other hand, inductors used in power amplifiers and large-size transistors can increase die area. Therefore, efficient, low-THD (Total harmonic distortion) and optimal-area power amplifiers are necessary for IoT applications. In [40] a new low-power and area transceiver structure utilized with merging both of class-D audio amplifier and power amplifier.

Higher efficiency as an important parameter guarantees durable operation of the power amplifiers, particularly in portable devices [4]. Also, linearity is another significant issue in power amplifier design [5]. Regarding these parameters, power amplifiers are classified into two categories. The first category consists of linear amplifiers that contain class-A, class-B, class-AB and class-C and the second category is switching amplifiers including class-D and class-E [6], [7], [8], [41]. The applications that require high efficiency cannot be realized by first group of power amplifiers. In contrast, the traditional class-E power amplifier is not suitable for high power consumption [9]. However, simplicity and higher efficiency of Class-E power amplifiers encourage designers to utilize them for IoT applications. Several class-E power amplifiers are introduced in [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21] and each of them are utilized with special techniques to improve the power amplifier characteristics. In [19] the inverse class-E power amplifier at sub-nominal condition is presented. Moreover, effect of the transistor parasitic elements on drain efficiency and maximum operational frequency was introduced in [19]. But, some drawback of inverse class-E PA such as effect of capacitor patristics is existed. In the conventional structure, an RF choke is employed between the supply voltage and switch transistor. This is recognized as an infinite DC feed or shunt capacitor architecture. These circuits are not proper for integrated design, since the available chokes do not have a high-quality factor inductor. Therefore, power consumption of this architecture is relatively high [22]. In the modified structure, a small inductor is utilized and eliminates choke without any shunt capacitance. This structure could not reach the desired specs, due to drain node capacitance [22]. A new switching mode CEPA is presented in [23]. In this paper, parallel capacitor and inductor are used in new architecture to have best performance. But in this paper, there is no accurate analysis for non-ideal effect of component. An analysis of CEPA is introduced in [24]. In this paper a new method for CEPA design is introduced that based on power consumption of each component. In this manner designer could optimize their design for power efficiency and power capability and if any other parameter is required this manner is not well. A neutralization technique is presented in [25] that improve power gain and reverse isolation. Moreover, the transmission line is used in this paper to have high power efficiency.

The power amplifier transistors should have a large size, so the capacitance between gate and drain becomes extremely large, which could be in the range of hundreds Femto-Farad. These extra capacitances decrease the gain and deteriorate stability. An interesting technique that resolve gain and stability problem is the use of cross coupling capacitor. In this manner, neutralized capacitors, attenuates positive feedback from drain to gate and thus, stability improves. Therefore, higher gains can be achieved without any concern for instability [26]. In addition, it was demonstrated that this technique increases the gain and improves the reverse isolation [25].

A number of watt-level power amplifiers were reported with over 40% power added efficiency (PAE) which utilized different CMOS technologies such as 0.8 and 0.35 µm [27], [28]. In [27], robustness against voltage stress was obtained; however, power dissipation was large. Combining positive feedback and the injection lock oscillator in class-E power amplifier configuration was utilized in [28]. This structure is sensitive to the voltage stress on the transistor. Therefore, delivering RF power for deep submicron CMOS power amplifier is still a challenge. The millimeter wide transistor is applied in order to drive sufficient current for watt-level output power [28], [29], [30].

Due to these constraints that exist in power amplifiers, we present a fully differential structure which uses complimentary CMOS cross couple pair configurations, in order to achieve high operating frequency, PAE and p_out. On the contrary, a capacitor cross coupling neutralization is applied to improve power gain and stability. Using capacitor cross coupling neutralization technique, gives the ability to overcome the area constraint which was caused by using capacitor and inductor. Small transistor size and low THD are obtained by applying fully differential Class-E and complementary structures, respectively.

The remaining part of the study is organized as follows: Section 2 describes a concise review of the Class-E power amplifier and cross coupling neutralization. Detail illustration of our proposed power amplifier circuit is described in Section 3. Experimental results are demonstrated in Section 4 and concluding remark is given in Section 5.