Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
Introduction
Non-volatile spintronic memories represent a promising knob to deal with the increased leakage power resulting from the scaling down of CMOS technology towards the end of Moore's law [[1], [2], [3], [4]]. In particular, spin-transfer torque magnetic random access memories (STT-MRAMs) based on perpendicular magnetic tunnel junctions (p-MTJs) are already in the market with potential improvement targeting low-power and high-speed operation, high density, high endurance, long data retention time, low fabrication cost, and easy integration with CMOS processes [[5], [6], [7]]. Thanks to the above properties, STT-MRAMs are actually considered as premier candidates for replacing conventional semiconductor-based cache memories at more scaled technology nodes [7]. However, one of the remaining challenges for a wider spread of STT-MRAMs is the reduction of their writing currents for both energy and area savings [8]. In this regard, one effective strategy concerns the use of double-barrier MTJs with two reference pinned layers (DMTJs) [[8], [9], [10], [11]] instead of conventional single-barrier MTJs (SMTJs).
Within the above context, this work investigates STT-MRAMs for cache applications based on p-MTJ and FinFET devices. More specifically, DMTJ-based STT-MRAMs implemented at nanoscale technology nodes from 28-nm down to 20-nm have been benchmarked against their SMTJ-based counterparts. This analysis has been carried out at different design abstraction levels exploiting a cross-layer simulation framework. The latter spreads from the device- up to the system-level passing through a circuit-level analysis for different memory bitcell configurations and a memory architecture-level analysis for various cache sizes. It is worth mentioning that this work extends the study presented in Ref. [12] by including temperature-dependent results at the device- and circuit-level, by expanding the architecture-level analysis at more scaled technology nodes (i.e. 24-nm and 20-nm), and by adding comparative analysis at the system-level.
This paper is organized as follows. Section 2 introduces the simulation framework used in this work. Section 3 discusses the comparative results obtained at different levels of abstraction. Finally, Section 4 summarizes the main conclusions of the work.
Section snippets
Device-to-system level simulation framework
As shown in Fig. 1, our simulation flow follows a bottom-up approach with four levels of abstraction: device-, circuit-, architecture-, and system-level.
At the device-level, perpendicular SMTJ and DMTJ devices featuring circular geometries have been considered (see Fig. 1(a)). The SMTJ consists of three layers: two ferromagnetic (FM) layers, i.e. the reference layer (RL) with a fixed magnetization orientation and the free layer (FL) with a variable magnetization orientation, which are separated
Simulation results and discussion
First, this section deals with the modeling of both transistor and p-MTJ devices for technology nodes from 28-nm down to 20-nm along with a preliminary comparative analysis between SMTJ and DMTJ at device-level. Then, it reports and discusses simulation results obtained at circuit-, architecture-, and system-level.
Conclusions
In this work, DMTJ-based STT-MRAMs addressed to cache applications have been benchmarked against their SMTJ-based counterparts while considering the effect of technology scaling (from 28-nm down to 20-nm node). Our study has been carried out by means of a cross-layer simulation framework, which includes four levels of abstraction: device-, circuit-, architecture-, and system-level. First, on-purpose developed SMTJ/DMTJ Verilog-A compact models along with a 0.8 V FinFET technology have been
CRediT authorship contribution statement
Esteban Garzón: Investigation, Formal analysis, Data curation. Raffaele De Rose: Validation, Writing - original draft, Writing - review & editing. Felice Crupi: Supervision, Writing - review & editing. Lionel Trojman: Visualization, Writing - review & editing. Giovanni Finocchio: Methodology, Funding acquisition. Mario Carpentieri: Methodology, Funding acquisition. Marco Lanuzza: Conceptualization, Supervision, Project administration, Funding acquisition.
Acknowledgment
This work was supported under the Grant 2019-1-U.0. (“Diodi spintronici rad-hard ad elevata sensitività - DIOSPIN”) funded by the Italian Space Agency (ASI) within the call “Nuove idee per la componentistica spaziale del futuro”.
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