Elsevier

Integration

Volume 75, November 2020, Pages 141-149
Integration

Time-domain writing architecture for multilevel RRAM cells resilient to temperature and process variations

https://doi.org/10.1016/j.vlsi.2020.07.001Get rights and content

Highlights

  • A multilevel write driver for memristive cells has been designed based on a time-domain operation.

  • In depth temperature analysis has been carried out to avoid the harmful effects on multilevel storage.

  • Additionally, the effect of process variation has been studied both for the 40 nm technology and the RRAM cells under study.

  • A reliable architecture has been proposed that is resilient to temperature and process variations.

  • A novel calibration procedure with its corresponding circuitry has been designed.

Abstract

The high potential of memristors as multilevel resistance devices is undermined by their highly non-linear behaviour and a strong dependency on different sources of variability (process, voltage, temperature…). Temperature fluctuations are specially harmful because small thermal variations may significantly modify the operation point of the device. For these reasons the circuitry required to accurately read or write multilevel devices is complex and area demanding, especially if multi-level storage is considered. This work addresses the problem of accurately writing a given resistance value in a memristive cell by using a time-domain architecture found on variable pulses. Temperature resiliency is achieved after performing an in depth analysis of the definition of the resistance levels in the presence of thermal variations. Furthermore, a calibration procedure has been conceived to make the writing circuitry resilient to device to device variations. Experimental results show that the proposed approach is valid for a wide temperature range.

Introduction

In 2008 the first nanoscale memristor was created by scientists at Hewlett-Packard laboratories [19]. Since then, extraordinary interest has been devoted to the development of such devices and related applications. Memristors offer exceptional size scalability, fast switching and low energy per resistance update [13]. Memristor technology can transform current computing and scientific research because these devices offer tunable resistance states that can be used both to store information and to perform computation, allowing logic and memory to be integrated in energy-efficient highly parallel architectures. These capabilities translate into the outstanding features of the memristors for non-volatile on-chip storage, in-memory computing and biologically inspired computing [20].

The potential achievements of memristive memories, also known as Resistive RAM or RRAM, are clear. However, the use of these memories is affected by serious drawbacks, mainly due to their complex physical mechanisms and to the fact of not having an established manufacturing process. Resistive devices suffer from device variability, high nonlinearity and instability in the resistance level. For these reasons the design of reliable circuits that support reading and writing for state-of-the-art memristive cells is complicated and expensive. The problem exacerbates for the case of multilevel storage. The accurate programming of a given resistance level in a multilevel cell (MLC) is hard to achieve. Resistance changes are extremely abrupt, what toughens the definition of multiple levels, specially in a wide range. This is the reason why elaborated architectures are required to fine-tune the MLC values [2,12]. There are proposals for multilevel writing based on the use of programming pulses with variable length or amplitude [15,18] that allow the extension of the multi-level capabilities of memristors. However, there is a serious drawback when using these schemes: the corresponding circuitry requires expensive hardware, like different voltage sources, that results in large area and complex operation. Additionally they produce long and variable writing times, what may be not suitable for certain applications, like neuromorphic computing. The same issues arise with write drivers based on feedback-loops [12].

The problem of accurately controlling the stored level becomes harder when the temperature comes into play. There are significant deviations of the resistance in the MLC when temperature varies. Very few works have dealt with this issue, actually none of the above mentioned works deals with thermal variations when writing the MLC. In this paper we present a time-domain driver that is able to accurately write different resistance levels in an MLC in the presence of temperature and device variations. We additionally propose a reading driver also based on time-domain processing. The proposed architecture takes advantage of built-in small thermal sensors to adapt the writing process to the real resistance characteristic of the cell. Finally, a calibration procedure has been conceived to tolerate device to device variations of the MLC resistance.

This paper is structured as follows. First we study some related works before introducing the memristor model that has been used. Next, the proposed time-domain approach to multilevel writing is described and the effects of temperature in the writing driver are analysed in depth, looking for the best definition of resistance levels. After that we describe the effects of process variations on the proposed driver and how to deal with them. Finally, experimental results are presented and some conclusions are drawn.

Section snippets

Related work

The problem of accurately writing a resistance value in memristors has been addressed by the scientific community since the very beginning. For the specific case of multilevel writing, the publication [12] in 2010 is one of the earliest works if not the first. In the paper the authors propose a writing and reading circuitry based on the idea of making a current flow through the memristor and a set of resistors obtaining a pair of reference voltages. These voltages are compared and a new current

Memristor model

There are multiple memristors types depending on materials, transport mechanisms, etc. Related to this large variety a myriad of models has appeared that try to mimic the current-voltage characteristics of the memristor. The work described here has been carried out using the physics-based RRAM Verilog-A model developed by P. Y. Chen and S. Yu at Arizona State University (ASU) [4,5]. This compact model describes the resistive switching mechanism by means of a simplified one-dimensional

Time-domain MLC writing

There are different options to move between the different levels when dealing with a multilevel device. A straight-forward approach would be to allow any transition between levels. The number of paths required in that situation for moving between m different levels is quadratic with m. This approach can be significantly improved if an intermediate point is added, the key-point [9], used as departure point from where to go whenever a change of level is desired.

We have chosen as key-point the

Temperature analysis

The behaviour of memristive cells is significantly modified in the presence of temperature variations. In this section we analyse how the variation of temperature changes the characteristic resistance curves of the memristor in a range from 0 °C to 100 °C. Fig. 5a shows the results of that simulation by means of the resistance written in the MLC using the proposed configurable pulse lengths for different simulation temperatures. It can be observed that when the temperature increases the

Process variations

The proposed writing driver has proven to work properly in the presence of temperature variations, but a deeper analysis is required when other source of variations comes into play, especially if we are dealing with emerging devices and nanometer technology nodes. To have a reliable driver the integrating circuitry must also tolerate device to device variation. Next we analyse process variations and we distinguish between the variations in the commercial 40 nm CMOS devices and the variability

Experimental results

All proposed circuits have been designed using a 40 nm commercial technology with different transistor families optimised to work at 1.1, 1.8, 2.5 and 3.3 V. The nominal voltages of the transistor models are 1.8 V (standard modules) and 3.3 V (analogue multiplexers). For 1T1R cells we have used minimum size nMOS transistors (40 nm, 120 nm) placed in series with the RRAM building the cell.

The total writing time is less than 90 ns when considering the worst case scenario. It corresponds to the

Conclusions

In this paper we have presented an architecture that is able to write a resistance value in memristors when they are used as multilevel memory cells (1T1R) resilient to temperature and process variations. Its working principle is based on the use of configurable lengths of the time pulse applied to the memristor. The design is resilient to temperature and process variations. We add extra hardware to sense the temperature, what guarantees a correct value is stored in the cell even when there are

Author statement

Amadeo de Gracia Herranz: conceived the presented and developed idea, contributed to the design of the circuits, the develop of the simulations and the mathematical analysis, discussed the results and contributed to the manuscript. Marisa López-Vallejo: conceived the presented and developed idea, supervised the implementation of the project, discussed the results and contributed to the manuscript.

References (20)

  • A. Bagheri-Soulla et al.

    A high-precision time-domain rram state control approach

    Microelectron. J.

    (2018)
  • S. Poblador et al.

    Investigation of the multilevel capability of tin/ti/hfo2/w resistive switching devices by sweep and pulse programming

    Microelectron. Eng.

    (2018)
  • M. Ramadan et al.

    Adaptive programming in multi-level cell reram

    Microelectron. J.

    (2019)
  • F. Alibart et al.

    High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm

    Nanotechnology

    (2012)
  • Y. Cassuto et al.

    Information-theoretic sneak-path mitigation in memristor crossbar arrays

    IEEE Trans. Inf. Theor.

    (2016)
  • P.Y. Chen et al.

    Compact modeling of rram devices and its applications in 1t1r and 1s1r array design

    IEEE Trans. Electron. Dev.

    (2015)
  • P.Y. Chen et al.

    RRAM Veriloga Model, arizona State University

    (2016)
  • Y.Y. Chen et al.

    Balancing set/reset pulse for > 1010 endurance in HfO2/Hf 1t1r bipolar rram

    IEEE Trans. Electron. Dev.

    (2012)
  • F. Garca-Redondo et al.

    Self-controlled multilevel writing architecture for fast training in neuromorphic rram applications

    Nanotechnology

    (2018)
  • F. Garca-Redondo et al.

    Reconfigurable writing architecture for reliable rram operation in wide temperature ranges

    IEEE Trans. Very Large Scale Integr. (VLSI) Syst.

    (2017)
There are more references available in the full text version of this article.

Cited by (0)

This work has been funded by the NEUROWARE project (PGC2018-097339) from the Ministry of Science and Innovation.

View full text