Elsevier

Integration

Volume 79, July 2021, Pages 107-115
Integration

Design of FIR filter ISOTA with the aid of genetic algorithm

https://doi.org/10.1016/j.vlsi.2021.03.005Get rights and content

Highlights

  • Design of finite impulse response (FIR) filter involving shift and only two additions (ISOTA) has been accomplished in this work.

  • FIR ISOTA filter has been designed with the aid of Genetic algorithm.

  • Performance of the designed filter has been evaluated in terms of frequency response, full adder count, memory unit and delay time.

  • Proposed FIR filter ISOTA has been implemented on Cyclone IV FPGA board.

  • Proposed design has finally been compared with state-of-the-art FIR ISOTA filters for the sake of completeness.

Abstract

The field of digital signal processing has been receiving justified attention over the years because of a number of reasons including sophisticated algorithms, high computational speed and wider area of applications. In connection to this, design of finite impulse response (FIR) filter has drawn the attention of researchers throughout the globe. A number of promising developments has been carried out over the last few decades which emphasize on the design of hardware efficient filter structure. In this paper, a new technique of FIR filter design has been addressed by virtue of genetic algorithm. Filter coefficients have been searched over the discrete space in such a way that the architecture consists of shifts and only two adders. As a matter of fact, the proposed FIR filter involving shift and only two additions (ISOTA) results in minimal hardware cost during its implementation. This has been illustrated by means of a few example filters in this work. Some of the recently proposed FIR ISOTA filters have also been taken for the purpose of comparison. Finally, the proposed filter has been implemented on Altera Cyclone IV FPGA board.

Introduction

Signal processing is one of the emerging areas under the banner of electrical engineering. The major focus remains on inspecting, customizing and synthesizing signals like sound, images, videos, etc. Broadly speaking, the domain of signal processing extends to vast application fields like wireless communication, speech processing, process control, sensor array processing, seismology, feature extraction, biological measurement and many others. The Subfields under the signal processing are roughly categorized as analog signal processing, digital signal processing (DSP), non-linear signal processing and statistical signal processing [1].

With the advancement in the field of signal processing, DSP and the mixed signal processing have become the most sought technologies today. Digital filter, being an important component in both these systems, is broadly classified into two categories, namely infinite impulse response (IIR) filter and finite impulse response filter (FIR) filter. Linear phase and inherent stability of FIR filter with bounded-input-bounded-output (BIBO) criterion clearly demarcate it from IIR filter [2]. The presence of internal feedback in the IIR filter structure can make it possible to respond for the indefinite period and thus can be uncontrollable at time.

From the design perspective, FIR digital filters are usually constructed with multipliers, adders and series of delay elements to create the output. In the past few decades, major focus of the researchers was to design the hardware efficient filters with the features that give rise to replacement of multiplier with the adders and shifters, reducing the computation time and area, lowering power consumption with better efficiency [3]. Direct presence of multiplier in the hardware design results in larger filter area and more power consumption which is really unbefitting in portable wireless devices like mobile phones, laptops, tablets etc.

One of the most efficient ways to reduce the hardware complexity of digital filter is to express the filter coefficients in the form of sums of signed-powers-of-two (SPT) [4]. Expressing the coefficients in such a manner allows the multipliers in the filter structure to be replaced by a small number of shifters and adders. This action results in noticeable improvement in the area and power consumption with better hardware efficiency.

Considering the fixed word length B of the DSP processor, the impulse response coefficient in SPT may have its general form likeh(n)=i=1Bsi2i,wheresi{1,0,1}

Common sub-expression elimination (CSE) technique basically searches for the common or identical expression (which evaluates to give same value) present in several equations [5]. In the research field of digital filter design, this is a common optimization technique dealing with the multiplication of input signal as a single variable with many constants (coefficients). This eliminates any redundancy involved during the computation of multiplication of input variable with coefficients. Here, the coefficients may remain in CSD format and the CSE technique searches for the common bit pattern that exists among the coefficients.

An alternative approach to CSE technique for the reduction of word length of the coefficients in FIR digital filter is differential coefficients method (DCM) [6]. In CSE technique, coefficients are directly multiplied with the input by avoiding the repetitive computation of common expression. On the other hand, instead of direct multiplication of coefficient, the adjacent coefficient difference is multiplied with the input in DCM. This leads to the requirement of fewer numbers of bits to encode the coefficients. This benefit gives rise to the reduction of word length of the filter resulting in lower arithmetic units. This method saves the memory units and power consumption as well

This article deals with the design and implementation of FIR filter involving shift and only two additions (ISOTA) with the help of genetic algorithm (GA). Difference between two consecutive coefficients is encoded as chromosome in the evolutionary programming. Performance of the resultant filter is evaluated by means of full adder count, memory units and delay time. Rest of the paper is organized as follows: Section II documents state-of-the-art research findings pertaining to the present area of research. Proposed algorithm is described in section III while results and discussions are presented in section IV. Finally, the paper is concluded in section V.

Section snippets

Literature review

This section elaborates different FIR filter design algorithms which have been proposed over the years to address the issue of hardware efficiency. The fact that the symmetricity in the coefficient of FIR digital filter leads to linearity in its phase is widely used in the analysis and design of DSP system [7]. Authors have mathematically established the equivalence between linear phase and symmetry of the taps in FIR filter. Uniqueness of the group delay for any decomposition amplitude-phase

Proposed algorithm

This work concentrates on the design of ISOTA filter with the aid of Genetic algorithm by selecting the best individual from the entire population which can closely resemble the ideal filter's frequency response. System function of the ideal FIR filter of length N with impulse response coefficients hd(n) can be written as:Hd(z)=n=0N1hd(n)zn

Frequency response of the said filter can easily be obtained by computing the z-transform on unit circle and is represented by:Hd(ω)=n=0N1hd(n)ejωn

Now,

Simulation results & discussions

Design of FIR filters ISOTA has been accomplished in this work with the aid of GA. Since the designed filters involve sum and only two additions, architecture of these filters essentially contain two arrays namely additive input array (AIA) and subtractive input array (SIA). In the proposed design, each of the filter coefficients contains at most one powers-of-two terms so as to distribute them amongst as more coefficients as possible. Irrespective of the sign of the coefficient, a particular

Conclusions

In this work, a new design strategy of FIR filter has been proposed using genetic algorithm technique. Main objective of this proposition is to reduce the hardware cost of the designed filter. In regard to this, FIR filter ISOTA structure has been considered. It has been found that the proposed GA-based algorithm is capable enough to realize filter specifications with relatively lower filter order. This has reduced the FA count and memory requirement to a significant extent. Delay time

Author statement

Abhijit Chandra: Conceptualization, Methodology, Formal analysis, Writing-original draft, Writing-review & editing, Visualization, Supervision. Amit Kumar: Investigation, Resources. Subhabrata Roy: Validation.

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

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