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Power Optimization in VLSI Layout: A Survey

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Abstract

This paper presents a survey of layout techniques for designing low power digital CMOS circuits. It describes the many issues facing designers at the physical level of design abstraction and reviews some of the techniques and tools that have been proposed to overcome these difficulties.

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  1. Department of EE-Systems, University of Southern California, Los Angeles, CA, 90089

    Massoud Pedram & Hirendu Vaishnav

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  1. Massoud Pedram
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  2. Hirendu Vaishnav
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Pedram, M., Vaishnav, H. Power Optimization in VLSI Layout: A Survey. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 15, 221–232 (1997). https://doi.org/10.1023/A:1007907110303

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