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Performance Modeling of System Architectures

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Abstract

Performance modeling of network architectures has been an integral part of network systems design for decades. As signal processing system architectures become more and more complex, models of computational performance are becoming an important part of the architectural design process. This paper will describe performance modeling, both in general, and within the context of the RASSP system design process.

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References

  1. IEEE Standard VHDL Language Reference Manual, IEEE Std 1076-1993, IEEE Customer Service, 445 Hoes Lane, P.O. Box 1331, Piscataway, New Jersey 08855-1331.

  2. C. Hein et al., “RASSP VHDL modeling terminology and taxonomy-Revision 1.0,” Proceedings 2nd Annual RASSP Conference, Arlington, VA, July 1995, pp. 273-281.

  3. J.H. Aylor, R. Waxman, B.W. Johnson, and R.D. Williams, “The integration of performance and functional modeling in VHDL,” in Performance and Fault Modeling with VHDL, J. Schoen (Ed.), Prentice-Hall, Englewood Cliffs, N.J., 1992.

    Google Scholar 

  4. S. Kumar, J.H. Aylor, B.W. Johnson, and W.A. Wulf, The Codesign of Embedded Systems: A Unified Hardware/Software Representation, Kluwer Academic Publishers, Dordrecht, The Netherlands, 1996.

    Book  Google Scholar 

  5. F. Rose, T. Steeves, and T. Carpenter, “VHDL performance models,” Proceedings 1st Annual RASSP Conference, Arlington, VA, Aug. 1994, pp. 60-70.

  6. T. Steeves et al., “Evaluating distributed multiprocessor designs,” Proceedings 2nd Annual RASSP Conference, Arlington, VA, July 1995, pp. 95-102.

  7. J. Shackleton and T. Steeves, “Advanced multiprocessor system modeling,” Proceedings Fall 1995 VIUF, Boston, MA, Oct. 1995, pp. 8.21-8.28.

  8. M. Meyassed, R. McGraw, J. Aylor, R. Klenke, R. Williams, F. Rose, and J. Shackleton, “Framework for the development of hybrid models,” Proceedings 2nd Annual RASSP Conference, Arlington, VA, July 1995, pp. 147-154.

  9. Mohanty, “An integrated design environment for rapid system prototyping, performance modeling and analysis using VHDL,” Masters Thesis, University of Cincinnati, Sept. 1994.

  10. Honeywell Technology Center, VHDL Performance Modeling Interoperability Guideline, Version 1.6, Nov. 1995. URL <http://rassp.scra.org/public/tb/honeywell/HONEYWELL-DOCS.html>

  11. E. Sternheim et al., Digital Design with Verilog HDL, Automata Publishing Company, pp. 5-28, 1990.

  12. J. Peterson, “Petri Nets,” Computing Surveys, Vol. 9, No. 3, pp. 223-252, Sept. 1977.

    Article  MathSciNet  MATH  Google Scholar 

  13. W.M. Zuberek, “Timed Petri Nets and preliminary performance evaluation,” Proceedings 7th Annual Symposium Computer Architecture, pp. 89-96, 1980.

  14. M.K. Molloy, “Performance analysis using stochastic Petri Nets,” IEEE Transactions on Computer, Vol. C-31, No. 9, pp. 913-917, Sept. 1982.

    Article  Google Scholar 

  15. M.A. Holliday and M.K. Vernon, “A generalized timed Petri Net for performance analysis,” IEEE Transactions on Software Engineering, Vol. SE-13, No. 12, Dec. 1987.

  16. C.K. Chang, Y. Chang, L. Yang, C. Chou, and J. Chen, “Modeling a real-time multitasking system in a timed PQ net,” IEEE Software, pp. 46-51, March 1989.

  17. D. Ferrari, Computer Systems Performance Evaluation, Prentice-Hall, Englewood Cliffs, NJ, 1978.

    Google Scholar 

  18. L. Kleinrock, Queuing Systems, Vol. 1: Theory, Wiley Publishing, New York, 1975.

    Google Scholar 

  19. G.S. Graham, “Queuing network models of computer system performance,” Computing Surveys, Vol. 10, No. 3, pp. 219-224, Sept. 1978.

    Article  Google Scholar 

  20. A.O. Allen, “Queuing models of computer systems,” IEEE Computer, pp. 13-24, April 1980.

  21. G. Balbo, S.C. Bruell, and S. Ghanta, “Combining queuing networks and generalized stochastic Petri Nets for solutions of complex models of system behavior,” IEEE Transactions on Computer, pp. 1251-1268, Oct. 1988.

  22. F. Hady, J.H. Aylor, R. Waxman, B.W. Johnson, and R.D. Williams, “Uninterpreted/Interpreted modeling of digital systems in a common simulation environment,” Department of Electrical Engineering, University of Virginia, Technical Report No. CSIS 881208.0, Dec. 8, 1988.

  23. C.U. Smith and R.R. Gross, “Technology transfer between VLSI design and software engineering: CAD tools and design methodologies,” Proceedings of the IEEE, Vol. 74, No. 6, pp. 875-885, June 1986.

    Article  Google Scholar 

  24. D.W. Franke and M.K. Purvis, “An overview of hardware/ software codesign,” International Symposium on Circuits & Systems, pp. 2665-2668, May 1992.

  25. G. Estrin, R.S. Fenchel, R.R. Razouk, and M.K. Vernon, ”SARA: Modeling, analysis, and simulation support for design of concurrent systems,” IEEE Transactions on Software Engineering, Vol. SE-12, No. 2, pp. 293-311, Feb. 1986.

    Article  Google Scholar 

  26. Scientific Engineering Software, Inc., SES/Workbench User's Guide, Austin, Texas, April 1989.

  27. G.A. Frank et al., “An architecture design and assessment system for software/hardware codesign,” Proceedings 22nd Design Automation Conference, pp. 417-424, 1985.

  28. M.B. Srivastava and R.W. Broderson, “Rapid-prototyping of hardware and software in a unified framework,” Proceedings of the International Conference on Computer-Aided Design, pp. 152-155, 1991.

  29. A. Kalavade and E.A. Lee, “A Hardware-software codesign methodology for DSP applications,” IEEE Design and Test, pp. 16-28, Sept. 1993.

  30. K. Jensen, “Colored Petri Nets: A high level language for system design and analysis,” in High-level Petri Nets: Theory and Application, K. Jensen and G. Rozenberg (Eds.), Springer-Verlag, Berlin, 1991, pp. 44-119.

    Chapter  Google Scholar 

  31. E. Cutright et al., A Handbook on the Unified Modeling Methodology Building Block Set, 2nd Edition, University of Virginia, Technical Report No. 910828.1, May 1993.

  32. C. Hein and D. Nasoff, “VHDL-based performance modeling and virtual prototyping,” Proceedings 2nd Annual RASSP Conference, Arlington, VA, July 1995, pp. 87-94.

  33. J. Pridmore and W. Schaming, “RASSP methodology overview,” Proceedings 1st Annual RASSP Conference, Arlington, VA, Aug. 1994, pp. 71-85.

  34. University of Tennessee, “PDS: The performance database server,” URL <http://performance.netlib.org/performance/html/ PDStop.html>

  35. B. Zuerndorfer and G. Shaw, “SAR processing for RASSP application,” Proceedings 1st Annual RASSP Conference, Arlington, VA, Aug. 1994, pp. 253-268.

  36. R. MacDonald, R. Williams, and J. Aylor, “An approach to unified performance and functional of complex systems,” IASTED Conference on Modeling and Simulation, Apr. 1995.

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Authors and Affiliations

  1. Honeywell Technology Center, Minneapolis, MN

    Fred Rose & John Shackleton

  2. Advanced Technology Laboratories, Lockheed Martin, Camden, NJ

    Carl Hein

Authors
  1. Fred Rose
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  2. John Shackleton
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  3. Carl Hein
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Rose, F., Shackleton, J. & Hein, C. Performance Modeling of System Architectures. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 15, 97–109 (1997). https://doi.org/10.1023/A:1007926522033

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