Skip to main content
SpringerLink
Log in

Clocking Optimization and Distribution in Digital Systems with Scheduled Skews

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

System performance can be improved by employing scheduled skews at flip-flops. This optimization technique is called skewed-clock optimization and has been successfully used in memory designs to achieve high operating frequencies. There are two important issues in developing this optimization technique. The first is the selection of appropriate clock skews to improve system performance. The second is to reliably distribute skewed clocks in the presence of manufacturing and environmental variations. Without the careful selection of clocking times and control of unintentional clock skews, potential system performance might not be achieved. In this paper a theoretical framework is first presented for solving the problem of optimally scheduling skews. A novel self-calibrating clock distribution scheme is then developed which can automatically track variations and minimize unintentional skews. Clocks with proper skews can be reliably delivered by such a scheme.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. H.B. Bakoglu, Circuits, Interconnection, and Packaging for VLSI, Addison-Wesley, 1990.

  2. H. Hsieh, W. Liu, C.T. Gray, and R. Cavin, “Concurrent timing optimization of latch-based digital systems,” International Conference on Computer Design, pp. 680-685, 1995.

  3. C.T. Gray, W. Liu, and R. Cavin III, Wave Pipelining: Theory and CMOS Implementations, Kluwer Academic Publisher, Oct. 1993.

  4. J. Neves and E. Friedman, “Design methodology for synthesizing clock distribution networks exploiting non-zero localized clock skew,” IEEE Transactions on VLSI Systems, Vol. 4, pp. 286-291, June 1996.

  5. J.P. Fishburn, “Clock skew optimization,” IEEE Transactions on Computers, Vol. 39, pp. 945-951, July 1990.

  6. M. Heshami and B. Wooley, “A 250-MHz skewed-clock pipelined data buffer,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 3, pp. 376-383, March 1996.

  7. H. Toyoshima, “A300-MHz 4-Mbwave-pipeline CMOS SRAM using a multi-phase PLL,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 11, pp. 1189-1202, Nov. 1995.

  8. R. Tsay, “An exact zero-skew clock routing algorithm,” IEEE Transactions on Computer-Aided Design, Vol. 12, No. 2, pp. 242-249, Feb. 1993.

  9. S. Pullela, N. Menezes, and L.T. Pillage, “Reliable non-zero skew clock trees using wire width optimization,” 30th Design Automation Conference, pp. 165-170, 1993.

  10. R. Watson and R. Iknaian, “Clock buffer chip with multiple target automatic skew compensation,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 11, pp. 1267-1276, Nov. 1995.

  11. E. Best, Phase Locked Loops: Theory, Design, and Applications, McGraw-Hill, c1984.

  12. N. Shenoy et al., “On the temporal equivalence of sequential circuits,” 29th Design Automation Conference, pp. 405-409, 1992.

  13. M.R. Garey and D.S. Johnson, Computers and Intractability, W.H. Freeman and Company, 1979.

  14. T.H. Cormen, C.E. Leiserson, and R.L. Rivest, Introduction to Algorithms, McGraw-Hill, 1990.

  15. M. Shoji, “Elimination of process-dependent clock skew in CMOS VLSI,” IEEE Transactions on Computers, Vol. C-39, No. 7, pp. 945-951, July 1990.

  16. J. Kang, W. Liu, and R. Cavin III, “A monolithic 625Mb/s data recovery circuit in 1.2 µm CMOS,” Custom Integrated Circuits Conference, pp. 463-465, March 1994.

  17. M.G. Johnson and E.L. Hudson, “A variable delay line PLL for CPU-Coprocessor synchronization,” IEEE Journal of Solid-State Circuits, pp. 1218-1223, 1988.

  18. C.T. Gray, W. Liu, W. van Noije, T. Hughes, and R. Cavin III, “A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution,” IEEE Journal of Solid-State Circuits, Vol. 29, No. 3, pp. 340-349, March 1994.

    Article  Google Scholar 

  19. H. Hsieh, Clocking Optimization and Distribution in Digital Systems with Scheduled Skews, Ph.D. Thesis, North Carolina State University, 1996.

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, 27695-7911

    Hong-Yean Hsieh, Wentai Liu & Paul Franzon

  2. Semiconductor Research Center, Research Triangle Park, NC, 27709

    Ralph Cavin III

Authors
  1. Hong-Yean Hsieh
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Wentai Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Paul Franzon
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Ralph Cavin III
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Hsieh, HY., Liu, W., Franzon, P. et al. Clocking Optimization and Distribution in Digital Systems with Scheduled Skews. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 16, 131–147 (1997). https://doi.org/10.1023/A:1007934922990

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1007934922990

Keywords

Search

Navigation