Abstract
In this paper, we propose a method for power optimization of digital signal processing (DSP) systems through reduction of circuit switching activity estimated from high levels in the synthesis hierarchy, namely at numerical and algorithmic levels. The optimization involves application of a numerical transformation called number-splitting on the system characteristic coefficients. The transformation alters the system characteristic coefficients while preserving the input/output relations. For each set of candidate coefficients, the corresponding signal flow-graph is constructed for evaluation of power consumption. First, the switching activity at all computation nodes of the graph are estimated using our novel activity transformation models, which quickly estimate the activity at the output of the adders and multipliers based on the activity at the inputs. Next, the activity at the inputs of each computation node are used to compute the average power consumption by that node, using our heuristic power estimators.
The optimization framework can be applied to hardware-dedicated bit-serial, nibble-serial, as well as programmable word-parallel architectures. We focus on hardware-dedicated bit-serial systems, and show that up to 35 percent savings in power is achievable.
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Nguyen, H.T., Chatterjee, A. & Roy, R.K. Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 18, 25–38 (1998). https://doi.org/10.1023/A:1007937209276
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DOI: https://doi.org/10.1023/A:1007937209276