Skip to main content
SpringerLink
Log in

Low Power Digital Frequency Conversion Architectures

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

State-of-the-art data communication systems make extensive use of digital hardware. Besides baseband modulation functions, also the frequency tuning functions are now being shifted from analog to digital implementation. Integration, cost and ease of programming are the primary motivations for doing this. This paper presents an alternative to the traditional digital frequency conversion architectures. The proposed architecture achieves low power as well as high speed operation, and achieves this dual goal by reducing programmability. A multi-rate filtering approach is used, which is applicable for both upconversion and downconversion of quadrature modulated data.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. W. Pugh and G. Boyer, “Broadband Access: Comparing Alternatives”, IEEE Commun. Mag., vol. 33, Aug. 1995, pp. 34–36.

    Article  Google Scholar 

  2. K. Kerpez and K. Sistanizadeh, “High Bit Rate Asymmetric Digital Communications Over Telephone Loops”, IEEE Trans. Commun., vol. 43, June 1995, pp. 2038–2049.

    Article  Google Scholar 

  3. C. Eldering, N. Himayat, and F. Gardner, “CATV Return Path Characterization for Reliable Communications”, IEEE Commun. Mag., vol. 33, Aug. 1995, pp. 62–69.

    Article  Google Scholar 

  4. Digital Video Broadcasting DVB Interaction channel for Cable TV Distribution Systems, ETS 300 800, European Telecommunications Standards Institute, February 1197.

  5. Data-Over-Cable Interface Specifications; Radio Frequency Interface Specification, SP-RFII01-970326, MCNS Holdings, L.P., March 1997.

  6. J. G. Proakis, Digital Communications”, 3rd ed., McGraw-Fill Series in Electrical and Computer Engineering, 1995.

  7. W.Webb and L. Hanzo, Modern Quadrature Modulation, New York: IEEE Press, 1994.

    Google Scholar 

  8. R. Baines, “The DSP Bottleneck”, IEEE Commun. Mag, vol. 33, May 1995, pp. 46–54.

    Article  Google Scholar 

  9. P.R.Gray and R.G. Meyer, “Future Directions in Silicon ICs for RF Personal Communications”, CICC Proceedings, 1995, pp. 83–90.

  10. H. Samueli, “The Design of Multiplierless FIR filters for Compensating D/A Converter Frequency Response Distortion”, IEEE Trans. Circuits and Syst., vol. 35, Aug. 1988, pp. 1064–1066.

    Article  MathSciNet  Google Scholar 

  11. R. Crochiere and L. Rabiner, “Interpolation of Signals-A tutorial Review”, Proc. IEEE, vol. 69, Mar. 1981, pp. 300–331.

    Article  Google Scholar 

  12. T. Laakso, V. Valimaki, M. Karjalainen, and U. Laine, “Splitting the Unit Delay”, IEEE Signal Processing Mag., vol. 13, Jan. 1996, pp. 30–60.

    Article  Google Scholar 

  13. J. McClellan and T. Parks, “A Computer Program for Designing FIR linear phase Digital Filters”, IEEE Trans. Audio. Electroacoust, vol. AU-21, Dec. 1973, pp. 506–526.

    Article  Google Scholar 

  14. L. K. Lau, R. Jain, H. Samueli, H. T. Nicholas III, and E. G. Cohen, “DDFSGEN: A Silicon Compiler for Direct Digital Frequency Synthesizers,” Journal of VLSI Signal Processing, vol. 4, 1992, pp. 213–216.

    Article  Google Scholar 

  15. L. K. Tan and H. Samueli, “A 200 MHz Quadrature Digital Synthesizer/Mixer in 0.8 µm CMOS”, IEEE J. Solid State Circ., vol. 30, March 1995, pp. 193–200.

    Article  Google Scholar 

  16. HSP45116 Numerically Controlled Oscillator/Modulator, Harris Semiconductor Data Sheet, May 1996.

  17. STEL-1172B CMOS NCO, Stanford Telecommunications Data Sheet, 1995.

  18. PDSP16350 I/Q Splitter/NCO, GEC Plessey Semiconductor Data Sheet, June 1996.

  19. W. Geurts, F. Catthoor, S. Vernalde, and H. De Man, Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications, Boston: Kluwer Academic Publishers, 1997.

    Book  MATH  Google Scholar 

  20. K. Hwang, Computer Arithmetic, NewYork: JohnWiley, 1979.

    Google Scholar 

  21. HSP50016 Digital Down Converter, Harris Semiconductor Data Sheet, December 1996.

  22. J. A. Wepman, “Analog-to-Digital Converters and their Applications in Radio Receivers”, IEEE Commun. Mag., vol. 33, May 1995, pp. 39–45.

    Article  Google Scholar 

  23. O. Mauss, “Bandpass Sampling”, Ph.D. thesis, chap. 6.1.2, RWTH Aachen, Lehrstuhl fur Integrierte Systeme der Signalverarbeitung.

Download references

Author information

Authors and Affiliations

  1. IMEC VZW, Kapeldreef 75, B-3001, Leuven, Belgium

    Patrick Schaumont, Serge Vernalde, Marc Engels & Ivo Bolsens

Authors
  1. Patrick Schaumont
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Serge Vernalde
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Marc Engels
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Ivo Bolsens
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Schaumont, P., Vernalde, S., Engels, M. et al. Low Power Digital Frequency Conversion Architectures. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 18, 187–197 (1998). https://doi.org/10.1023/A:1008092014351

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1008092014351

Keywords

Search

Navigation