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Design and Implementation of the PAPRICA Parallel Architecture

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Abstract

In this paper PAPRICA, a massively parallel coprocessor devoted to the analysis of bitmapped images is presented considering first the computational model, then the architecture and its implementation, and finally the performance analysis. The main goal of the project was to develop a subsystem to be attached to a standard workstation and to operate as a specialized processing module in dedicated systems. The computational model is strongly related to the concepts of mathematical morphology, and therefore the instruction set of the processing units implements basic morphological transformations. Moreover, the specific processor virtualization mechanism allows to handle and process multiresolution data sets. The actual implementation consists of a mesh of 256 single bit processing units operating in a SIMD style and is based on a set of custom VLSI circuits. The architecture comprises specific hardware extensions that significantly improved performances in real-time applications.

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Authors and Affiliations

  1. Dipartimento di Ingegneria dell'Informazione, Università di Parma, Italy

    A. Broggi & G. Conte

  2. Dipartimento di Elettronica, Politecnico di Torino, Italy

    F. Gregoretti, C. Sansoè, R. Passerone & L.M. Reyneri

Authors
  1. A. Broggi
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  2. G. Conte
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  3. F. Gregoretti
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  4. C. Sansoè
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  5. R. Passerone
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  6. L.M. Reyneri
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Broggi, A., Conte, G., Gregoretti, F. et al. Design and Implementation of the PAPRICA Parallel Architecture. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 19, 5–18 (1998). https://doi.org/10.1023/A:1008095714465

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