Abstract
This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.
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Lightbody, G., Walke, R., Woods, R. et al. Linear QR Architecture for a Single Chip Adaptive Beamformer. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 24, 67–81 (2000). https://doi.org/10.1023/A:1008118711904
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DOI: https://doi.org/10.1023/A:1008118711904