Abstract
This paper presents architectural and algorithmic approaches for achieving high-speed CORDIC processing in both of the two operating modes: vectoring and rotation. For vectoring mode CORDIC processing, a modified architecture is proposed, which aims at reduction of computation time by overlapping the stages for redundant addition and selection of rotation direction. In addition, a novel rotation direction prediction scheme for rotation mode CORDIC is presented. The method is based on approximation of the binary angle input to a number with the arctangent weights (tan−1 2−i). The implementation is designed to keep the fast timing characteristics of redundant arithmetic in the x/y path of the CORDIC processing. The characteristics are analyzed with respect to latency time and area, and compared with those obtained by conventional CORDIC implementations. The results show that the proposed techniques reduce not only the block latency but also the overall computation time. Thus, they achieve higher throughput in pipelining.
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Kwak, JH., Choi, J.h. & Swartzlander, E.E. High-Speed CORDIC Based on an Overlapped Architecture and a Novel σ-Prediction Method. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 25, 167–177 (2000). https://doi.org/10.1023/A:1008123124150
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DOI: https://doi.org/10.1023/A:1008123124150