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Aggressive Dynamic Execution of Decoded Traces

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Abstract

In this paper, we consider the increased performance that can be obtained by using, in concert, three previously proposed enhancements. These enhancements are aggressive dynamic (run time) instruction scheduling, the reuse of decoded instructions, and trace scheduling (both aggressive dynamic instruction scheduling and decoded instruction reuse have been used in commercial systems). We show that these three enhancements complement and support one another. Hence, while each of these enhancements has been shown to have merit in its own right, when used in concert, we claim the overall advantage is greater than that obtained by using any one singly. To support this claim, we present the results from running benchmarks representing several common multimedia kernels. Subsequent simulations show results of 7.3 instructions completed per cycle for the best-performing benchmark for a reasonably aggressive microarchitecture that combines trace scheduling of decoded instructions (i.e., decoded traces) with aggressive dynamic execution.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA, 16802

    Benjamin Bishop, Robert M. Owens & Mary Jane Irwin

  2. Department of Mathematics and Computer Science, Goucher College, Baltimore, MD, 21204

    Thomas P. Kelliher

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  1. Benjamin Bishop
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  2. Thomas P. Kelliher
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  3. Robert M. Owens
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  4. Mary Jane Irwin
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Bishop, B., Kelliher, T.P., Owens, R.M. et al. Aggressive Dynamic Execution of Decoded Traces. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 22, 65–75 (1999). https://doi.org/10.1023/A:1008125919892

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  • DOI: https://doi.org/10.1023/A:1008125919892

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