Abstract
In this paper, we first present a reconfigurable architecture template for low-power digital signal processing, and then an energy conscious design methodology to bridge the algorithm to architecture gap. The energy efficiency of such an architecture and the effectiveness of the methodology are demonstrated in case study implementations targeting baseband voice processing and digital signal processing.
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Wan, M., Zhang, H., George, V. et al. Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 28, 47–61 (2001). https://doi.org/10.1023/A:1008159121620
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DOI: https://doi.org/10.1023/A:1008159121620