Abstract
This paper addresses the general problem of module level test ofassembled Multi-Chip Modules (MCMs) and specifically the performancetest of such modules. It presents a novel solution based-on built-in self-test (BIST). This solutionaugments the conventional single-chip BIST approach, which is used to produce individual good dies, to an effective multi-chip BIST solution. The multi-chip BIST puts the entire module in a self-test mode. The self-test mode not only provides effective detection of static and dynamic faults, but also identifies the failed elements, i.e., bad dies or substrate. The multi-chip self-test scheme is based on pseudo-random test generation and uses multi-signature evaluation. The hardware design ofmulti-chip and single-chip self-test blocks is combined under one common architecture called the Dual BIST Architecture. The paper introduces the Dual BIST Architecture and demonstrates a set of design configurations to implement it. The presented BIST solution provides a reliable static and dynamic test at the module as well as the bare die levels.
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Y. Zorian, “A Structured Testability Approach for Multi-Chip Modules Based on BIST and Boundary-Scan,” IEEE Trans. on Components, Packaging, and Manufacturing technology: Advanced Packaging, Part B, Vol. 17, No.3, pp. 283–290, Aug. 1994.
Y. Zorian and H. Bederr, “Designing Self-Testable MultiChip Modules,” Proc. of the European Design and Test Conference, 1996, pp. 181–185.
Y. Zorian, “A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary Scan,” Proceedings of IEEE ICCD, 1992, pp. 59–66.
V.D. Agrawal, C.J. Lin, P. Rutkowki, S. Wu, and Y. Zorian, “BIST for Digital Integrated Circuits,” AT&T Technical Journal, pp. 30–40, March/April 1994.
N. Jarawala, “Designing Dual Personality IEEE 1149.1 Compliant Multi-Chip Modules,” ITC, pp. 446–455, 1994.
G. Messner et al., “Thin Film Mutichip Modules,” A Technical Monograph of the International Society for Hybrid Microelectronics, 1992.
A. Doane and P.D. Franzon, Multi-Chip Module Technologies and Alternatives—The Basics, Van Nostrand Reinhold, 1993.
Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices,” Proc. of 11th IEEE VLSI Test Symposium, Atlantic City, 1993, pp. 4–9.
C.J. Lin, Y. Zorian, and S. Bhawmik, “PSBIST: A Partial-Scan Based Built-In Self-Test Scheme,” Proc. IEEE Int’l Test Conference, Oct. 1993, pp. 507–516.
Y. Zorian, “A Structured Approach to Macrocell Testing Using Built-In Self-Test,” Proc. IEEE Custom Integrated Circuits Conference, Boston, 1990, pp. 28.3.1–28.3.4.
M. Nicolaidis, “An Efficient Built-In Self-Test Scheme for Functional Test of Embedded RAMs,” Proc. 15th Int’l Symp. on Fault-Tolerant Computing, June 1985, pp. 118–123.
Y. Zorian and A. Ivanov, “An Effective BIST Scheme for ROMs,” IEEE Trans. on Computers, Vol. 41, No.5, pp. 646–653, May 1992.
Y. Zorian and A.J. van de Goor, “An Effective BIST Scheme for Ring-Address FIFOs,” Proc. Int’l Test Conference, Oct. 1994, pp. 378–387.
D. Gizopoulos, A. Paschalis, and Y. Zorian, “An Effective BIST Scheme for Booth Multipliers,” Proc. Intl. Test Conference, 1995, pp. 824–833.
D. Gizopoulos, A. Paschalis, and Y. Zorian, “An Effective BIST Scheme for Datapath,” Proc. Intl. Test Conference, 1996, pp. 76–85.
“IEEE Standard Test Access Port and Boundary-Scan Architecture,” IEEE Std. 1149.1-1990, IEEE Standards Office, NJ, May 1990.
J. Savir, “At-Speed Test is not Necessarily an AC Test,” IEEE Int’l Test Conference, 1991, pp. 722–728.
C. Dufaza and Y. Zorian, “On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs,” Proc. of European Design & Test Conference, 1997.
H.N. Scholz, D.R. Aadsen, and Y. Zorian, “A Method for Delay Fault Self-Testing of Macrocells,” Proc. of Int’l Test Conference, 1993.
C. Stroud, “Built-In Self-Test for High-Speed Data-Path Circuitry,” Proc. of Int’l Test Conference, Oct. 1991, pp. 47–56.
L. Whetsel, “Event Qualification-A Gateway to At-Speed System Testing,” Proc. IEEE Int’l Test Conference, 1990, pp. 135–141.
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Zorian, Y., Bederr, H. An Effective Multi-Chip BIST Scheme. Journal of Electronic Testing 10, 87–95 (1997). https://doi.org/10.1023/A:1008226715929
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DOI: https://doi.org/10.1023/A:1008226715929