Abstract
A hierarchical VLSI fault tracing method is proposed which isapplicable to the case where only CAD layout data is available in theCAD-linked electron beam test system. The CAD layout data is assumedto be hierarchically structured. The method uses the expansion of apreviously proposed integrated algorithm which combines atransistor-level fault tracing algorithm and a successive circuitextraction from a non-hierarchically or a flat structured CAD layoutdata. The method allows us to trace a fault hierarchically from thetop level cell to the lowest primitive cell and from the primitivecell to the transistor-level circuit in a consistent mannerindependent of circuit functions even when the cell data and thetransistor-level circuit data exist in a level as a mixture. Anapplication of the method to a hierarchically structured CMOS modellayout with about 600 transistors shows its validity.
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Miura, K., Nakamae, K. & Fujioka, H. Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System. Journal of Electronic Testing 10, 255–269 (1997). https://doi.org/10.1023/A:1008271709747
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DOI: https://doi.org/10.1023/A:1008271709747