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Compaction of IDDQ Test Sequence Using Reassignment Method

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Abstract

IDDQ testing is an effective method for detecting short faults of CMOS circuits. Since IDDQ testing requires the measurement of current, the testing time of IDDQ testing is longer than that of logical testing. In this paper, we proposed an IDDQ test compaction method for internal short faults of gates in sequential circuits by using the reassignment method of signal values. Experimental results show that test sequences generated by weighted random vectors can be reduced to short sequences with less computation time.

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References

  1. Y.K. Malaiya and S.Y.H. Su, “A new Fault Modeling and Testing Technique for CMOS Devices,” Proc. Int. Test Conf., 1982, pp. 25-34.

  2. S. Chakravarty and P.J. Thadikaran, “Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits,” Proc. VLSI Test Symp., 1993, pp. 25-32.

  3. E. Isern and J. Figueras, “Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits,” Proc. Int. Test Conf., 1993, pp. 73-82.

  4. R.S. Reddy, I. Pomeranz, S.M. Reddy, and S. Kajihara, “Compact Test Generation for Bridging Faults under IDDQ Testing,” Proc. VLSI Test Symp., 1995, pp. 310-316.

  5. T. Lee, I.N. Haji, E.M. Rundnick, and J.H. Patel, “Genetic-Algorithm-Based Test Generation for Current Testing of Bridging Faults in CMOS VLSI Circuits,” Proc. VLSI Test Symp., April 1996, pp. 456-462.

  6. T. Maeda, Y. Higami, and K. Kinoshita, “Test Generation for Sequential Circuits under IDDQ Testing,” IEICE Trans. Inf. & Syst., Vol. E81-D, No. 7, 1998.

  7. T.M. Niermann and J.H. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” Proc. European Design Automation Conf., 1991, pp. 214-218.

  8. F. Brglez, D. Bryant, and K. Kozminski, “Combination Profiles of Sequential Benchmark Circuits,” Proc. Int. Symposium on Circuits and Systems, 1989, pp. 1929-1934.

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Authors and Affiliations

  1. Department of Applied Physics, Osaka University, Osaka, Japan

    Toshiyuki Maeda & Kozo Kinoshita

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  1. Toshiyuki Maeda
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  2. Kozo Kinoshita
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Maeda, T., Kinoshita, K. Compaction of IDDQ Test Sequence Using Reassignment Method. Journal of Electronic Testing 16, 243–249 (2000). https://doi.org/10.1023/A:1008343431975

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  • DOI: https://doi.org/10.1023/A:1008343431975

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