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Hybrid Fault Simulation for Synchronous Sequential Circuits

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Abstract

We present a fault simulator for synchronous sequential circuits that combines the efficiency of three-valued logic simulation with the exactness of a symbolic approach. The simulator is hybrid in the sense that three different modes of operation—three-valued, symbolic and mixed—are supported. We demonstrate how an automatic switching between the modes depending on the computational resources and the properties of the circuit under test can be realized, thus trading off time/space for accuracy of the computation. Furthermore, besides the usual Single Observation Time Test Strategy (SOT) for the evaluation of the fault coverage, the simulator supports evaluation according to the more general Multiple Observation Time Test Strategy (MOT). Numerous experiments are given to demonstrate the feasibility and efficiency of our approach. In particular, it is shown that, at the expense of a reasonable time penalty, the exactness of the fault coverage computation can be improved even for the largest benchmark functions.

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Authors and Affiliations

  1. Institute of Computer Science, Albert-Ludwigs-University Freiburg, Am Flughafen 17, 79106, Freiburg im Breisgau, Germany

    Bernd Becker & Martin Keim

  2. Fachhochschule Trier, Campus Birkenfeld, University of Applied Sciences, PO Box 13 80, 55761, Birkenfeld, Germany

    Rolf Krieger

Authors
  1. Bernd Becker
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  2. Martin Keim
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  3. Rolf Krieger
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Becker, B., Keim, M. & Krieger, R. Hybrid Fault Simulation for Synchronous Sequential Circuits. Journal of Electronic Testing 15, 219–238 (1999). https://doi.org/10.1023/A:1008376522451

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