Abstract
A unified approach to tackle the characterization of the floating gate defect in analog and mixed-signal circuits is introduced. An electrical level model of the defective circuit is proposed extending previous models used effectively in the digital domain. The poly-bulk, poly-well, poly-power rail and metal-poly capacitances are significant parameters in determining the behavior of the floating gate transistor. The model is used to analyze the feasibility of testing a simple analog cell with the floating gate defects through the observation of the quiescent current consumption and the dynamic behavior.
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Brosa, A.M., Figueras, J. Characterization of Floating Gate Defects in Analog Cells. Journal of Electronic Testing 14, 23–31 (1999). https://doi.org/10.1023/A:1008388903741
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DOI: https://doi.org/10.1023/A:1008388903741