Abstract
We formulate several device timing characteristics, and introduce the concept of separation bounds to model devices' waveform timing specifications. Separation bounds are used to verify that the produced timings of one device's signals satisfy the required timings of another device to which it is to be connected. We show that even if we know the bounds on two pairs of signal events, say (u, v) and (v, w), we cannot always deduce the correct bounds on (u, w). However, we show that the shortest path method proposed in [4]—to deduce tight constraints from a partial specification—is safe, in the sense that an affirmative answer to satisfiability is trustworthy while a negative answer may be pessimistic.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
J. Benkoski, E. Vanden Meersch, L. Claesen, and H. De Man, “Efficient algorithms for solving the false path problem in timing verification,” IEEE International Conference on Computer-Aided Design, ICCAD-87, Santa Clara, California, pp. 44–47, Nov. 1987.
G. Borriello, “A new interface specification methodology and its application to transducer synthesis,” Ph.D. Thesis, Computer Science Division, EECS, University of California, Berkeley, May 1988.
D. Brand and V. Iyengar, “Timing analysis using functional relationships,” IEEE International Conference on Computer-Aided Design, ICCAD-86, Santa Clara, California, pp. 125–129, Nov. 1986.
J.A. Brzozowski, T. Gahlinger, and F. Mavaddat, “Consistency and satisfiability of waveform timing specifications,” Networks, Vol. 21, pp. 91–107, 1991.
E. Cerny and K. Khordoc, “Interface specification with conjunctive timing constraints: Realizability and compatibility,” Second AMAST Workshop on Real-Time Systems, Bordeaux, France, June 1995.
T. Gahlinger, “Coherence and satisfiability of waveform timing specifications,” Ph.D. Thesis, Department of Computer Science, University of Waterloo, Waterloo, 1989.
R.B. Hitchcock, “Timing verification and the timing analysis program,” 19th Design Automation Conference, IEEE, pp. 594–604, 1982.
T.I. Kirkpatrick and N.R. Clark, “PERT as an aid to logic design,” IBM Journal of Research and Development, pp. 135–141, March 1966.
K. McMillan and D.L. Dill, “Algorithms for interface timing verification,” 1992 IEEE International Conference on Computer Design: VLSI in Computers and Processors, IEEE Computer Society, 1992.
P. Rony, “Interfacing fundamentals: Timing diagram conventions,” Computer Design, pp. 152–153, Jan. 1980.
A. Ruehli and D.L. Ostapko, “VLSI Circuit analysis, timing verification and optimization,” in Fichter and Morf (Eds.), VLSI CAD Tools and Applications, Kluwer Publ., Boston, pp. 129–146, 1987.
J. Springer, “Making sense out of delay specs in semiconductor memories,” Electronics, pp. 82–88, Oct. 1971.
Toshiba, Inc., MOS Memory Products Databook 1983–1984, 1984.
P. Vanbekbergen, G. Goossens, and H. De Man, “Specification and analysis of timing constraints in signal transition graphs,” European DAC, 1992.
C. Wiatrowski and C. House, Logic Circuits and Microcomputer Systems, McGraw-Hill, 1980.
Zilog, Inc., 1982/1983 Data Book, 1983.
Rights and permissions
About this article
Cite this article
Mavaddat, F., Gahlinger, T. On Deducing Timing Constraints in the Verification of Interfaces. Formal Methods in System Design 12, 223–239 (1998). https://doi.org/10.1023/A:1008626616397
Issue Date:
DOI: https://doi.org/10.1023/A:1008626616397