Abstract
A data flow machine is said to be synchronized if for any vertex u in the underlying data flow graph, all inputs to vertex u arrive at the same time. An unsynchronized data flow machine with an acyclic underlying data flow graph can be transformed into a synchronized system by adding unit delay buffers to the system. This synchronization process can increase pipelining and throughout. Since the addition of delay buffers introduces hardware and area costs, it is desirable to insert the minimum number of delay buffers to synchronize a given data flow machine. Due to important applications in computer design, various delay buffer minimization problems have been studied by many researchers. Several optimal algorithms and heuristic algorithms have been proposed for slightly different models. In this paper, we introduce the concept of extensions of a directed acyclic graph to generalize and formalize several delay buffer minimization problems studied in the literature and present a polynomial time algorithm for computing the minimum delay buffer synchronization of a given data flow machine. Examples are provided to illustrate our algorithm and to show that our algorithm requires fewer delay buffers than previously published optimal algorithms for various models.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
J.A. Bondy and U.S.R. Murty, Graph Theory with Applications, Macmillan: London, 1976.
E. Boros, P.L. Hammer, and R. Shamir, “A polynomial algorithm for balancing acyclic data flow graphs,” IEEE Transactions on Computers, vol. 41, pp. 1380–1385, 1992.
P. Camion, “Modules unimodularies,” Journal of Combinatorial Theory, vol. 4, pp. 301–362, 1968.
P.R. Chang and C.S.G. Lee, “A decomposition approach for balancing large-scale data flow graphs,” IEEE Transactions on Computers, vol. 39, pp. 34–46, 1990.
J.B. Dennis and R.G. Gao, “Maximum pipelining of array operations on static data flow machine,” in 1983 International Conference on Parallel Processing, August 1983, pp. 331–334.
X. Hu, R.G. Harber, S.C. Bass, and Geo, “Minimizing the number of delay buffers in the synchronization of pipelined systems,” in 28th ACM/IEEE Design Automation Conference, 1991, pp. 758–763.
H.T. Kung and M. Lam, “Wafer-scale integration and two-level pipelined implementation of systolic arrays,” Journal of Parallel and Distributed Computing, vol. 1, pp. 32–63, 1984.
C.E. Leiserson and J.B. Saxe, “Retiming synchronous circuitry,” Algorithmitica, vol. X, pp. 5–35, 1991.
C.H. Parpadimitriou and K. Steiglitz, Combinational Optimization: Algorithms and Complexity, Prentice-Hall, Inc.: Englewood Cliffs, New Jersey, 1982.
D.K. Pradhan, M. Chatterjee, and S. Banerjee, “Buffer assignment for data driven architectures,” in Proceeding of the International Conference on Computer-Aided Design, 1993, pp. 665–668.
N.V. Shenoy, R.K. Brayton, and A.L. Sangiovanni-Vincentelli, “Minimum padding to satisfy short path constraints,” in Proceeding of the International Conference on Computer-Aided Design, 1993, pp. 156–161.
S.Z. Sun, D.H.C. Du, and G.L. Xue, “Achieving the shortest clock period by inserting the minimum amount of delay,” Lecture Notes in Computer Science, vol. 834, pp. 669–677, 1994.
S.Z. Sun, D.H.C. Du, and G.L. Xue, “Efficient algorithms for delay buffer minimization problem,” TR 94–23, Computer Science Department, University of Minnesota, 1994.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Xue, G., Sun, S., Du, D.H. et al. An Efficient Algorithm for Delay Buffer Minimization. Journal of Combinatorial Optimization 4, 217–233 (2000). https://doi.org/10.1023/A:1009850721462
Issue Date:
DOI: https://doi.org/10.1023/A:1009850721462