Abstract
This paper presents the implementation of a fault detection and correction technique used to design a robust 8051 micro-controller with respect to a particular transient fault called Single Event Upset (SEU). A specific study regarding the effects of a SEU in the micro-controller behavior was performed. Furthermore, a fault tolerant technique was implemented in a version of the 8051. The VHDL description of the fault-tolerant microprocessor was prototyped in a FPGA environment and results in terms of area overhead, level of protection and performance penalties are discussed.
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References
ALTERA Data Book 1995. Altera Corporation, March 1995.
A. Benso, P. Prinetto, M. Rebaudengo, and M. Sonza Reorda, “A Fault Injection Environment for Microprocessor-Based Boards,” Proc. IEEE International Test Conference, Sept. 1998, pp. 768-773.
S. Buchner, M. Olmos, R. Velazco, Ph. Cheynet, D. McMorrow, J. Mellinger, R. Ecoffet, and J.D. Muller, “Pulsed Laser Validation of Recovery Mechanisms of Critical SEE's in an Artificial Neural Network System,” IEEE Transactions of Nuclear Science, vol. 45 (issue 3 part 3), pp. 1501-1507, June 1998.
L. Carro, G. Pereira, and A. Suzin, “Prototyping and Reengineering of Microcontroller-Based Systems,” Proc. IEEE Rapid Systems Prototyping Workshop, Greece, June 1996, pp. 178-182.
P. Chow et al., “The Design of an SRAM-Based Field Programmable Gate Array—Part II: Circuit Design and Layout.” IEEE Transactions on VLSI, vol. 7,no. 3, pp. 321-330. Sept. 1999.
E.F. Cota, M.R. Krug, M. Lubaszewski, L. Carro, and A. Susin, “Implementing a Self-Testing 8051 Microprocessor,” Proc. 12th Symposium on Integrated Circuits and Systems Design, Los Alamitos: IEEE Computer Society, Sept. 1999, pp. 202-205.
Embedded Microcontrollers, Intel Datasheet, 1994.
IBM. SOI Technology: IBM's Next Advance in Chip Design. In: http://www.ibm.com (Jan. 2000).
R. Katz, R. Barto, and H. Tiggeler, “Sequential Circuit Design for Spaccborne and Critical Electronics,” Military and Aerospace Applications of Programmable Devices and Technologies, USA, Sept. 2000.
Z. Kohavi, Switching and Finite Automata Theory, New York, McGraw-Hill, 1970.
F.G. Lima, S. Rezgui, E. Cota, L. Carro, M. Lubaszewski, R. Velazco, and R. Reis, “Designing and Testing a Radiation Hardened 8051-Like Micro-controller,” Military and Aerospace Applications of Programmable Devices and Technologies, USA, Sept. 2000 (Submitted to the Journal of Space Rockets, special issue on MAPLD).
T. Ma and P. Dressendorfer, Ionizing Radiation Effects in MOS Devices and Circuits, New York, Wiley Eds., 1989.
E. Normand, “Single Event Upsets at Ground Level,” IEEE Transactions on Nuclear Science, vol. 43,no. 6, Dec. 1996.
R. Velazco, Ph. Cheynet, K. Beck, L. Peters, M. Olmos, J.-C. Rubio, R. Ecoffet, and J. Cabestany, “Radiation Tolerance of a Fuzzy Controller,” Engineering of Intelligent Systems (EIS'98), Feb. 1998.
R. Velazco, S. Rezgui, Ph. Cheynet, A. Bofill, and R. Ecoffet, “THESIC: A Testbed Suitable for the Qualification of Integrated Circuits Devoted to Operate in Harsh Environment,” IEEE European Test Workshop (ETW'98), pp. 89-90, May 1998.
R. Velazco, S. Rezgui, and R. Ecoffet, “Predicting Error Rate for Microprocessor-Based Digital Architectures Through C.E.U. (Code Emulating Upsets) Injection,” IEEE Transactions on Nuclear Science, vol. 47,no. 6, pp. 2405-2236, Dec. 2000.
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Cota, É., Lima, F., Rezgui, S. et al. Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults. Journal of Electronic Testing 17, 149–161 (2001). https://doi.org/10.1023/A:1011125927317
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DOI: https://doi.org/10.1023/A:1011125927317