Abstract
This article presents PAPRICA-3, a VLSI-oriented architecture for real-time processing of images and its implementation on HACRE, a high-speed, cascadable, 32-processors VLSI slice. The architecture is based on an array of programmable processing elements with the instruction set tailored to image processing, mathematical morphology, and neural networks emulation. Dedicated hardware features allow simultaneous image acquisition, processing, neural network emulation, and a straightforward interface with a hosting PC.
HACRE has been fabricated and successfully tested at a clock frequency of 50 MHz. A board hosting up to four chips and providing a 33 MHz PCI interface has been manufactured and used to build BEATR IX, a system for the recognition of handwritten check amounts, by integrating image processing and neural network algorithms (on the board) with context analysis techniques (on the hosting PC).
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References
R.M. Bozinovic and S.N. Srihari, "Off-line Cursive Script Word Recognition," IEEE Trans. on PAMI, vol. 11, 1989, pp. 68–83.
H.L. Teulings,"Invariant Handwriting Features Useful in Cur-sive-Script Recognition," in Fundamentals in Handwriting Recognition, S. Impedovo (Ed.), Berlin: Springer-Verlag, 1993, pp. 179–198.
B. Lazzerini, L.M. Reyneri, F. Gregoretti, and A. Mariani, "High-Speed Recognition of Handwritten Amounts on Italian Checks," Knowledge-Based Intelligent Techniques in Character Recognition, L.C. Jain and B. Lazzerini (Eds.), Florida: CRC Press, 1999, pp. 167–189.
J. Serra, Image Analysis and Mathematical Morphology, Aca-demic Press, London: 1992.
S. Haykin, Neural Networks: A Comprehensive Foundation, New York: Mc Millan College Publishing Company, 1994.
F. Gregoretti, L.M. Reyneri, C. Sanso´e, and L. Rigazio, "A Chip Set Implementation of a Parallel Cellular Architecture," Micro-processing and Microprogramming, vol. 35, Amsterdam (NL): North-Holland, 1992, pp. 417–425.
A. Broggi, G. Conte, F. Gregoretti, C. Sanso´e, and L.M. Reyneri, "The Evolution of the PAPRICA System," Integrated Computer-Aided Engineering, vol. 4, no. 2, New York (NY): John Wiley & Sons, 1997, pp. 114–136.
A. Broggi, G. Conte, F. Gregoretti, C. Sanso´e, R. Passerone, and L.M. Reyneri, "Design and Implementation of the PAPRICA. Parallel Architecture," Journal of VLSI Signal Processing, vol. 19, 1998, Amsterdam (NL): Kluwer Academic, pp. 5–18.
N. Yamashita, T. Kimura, Y. Fujita, Y. Aimoto, T. Manbe, S. Okazaki, K. Nakamura, and M. Yamashina, "A 3.84 GIPS Inte-grated Memory Array Processor with 64 Processing Elements and a 2-MB SRAM," IEEE Journal of Solid-State Circuits, vol. 29, no. 11, 1994, pp. 1336–1342.
H.M. Chang, M.H. Sunwoo, and T. Cho, "Implementation of a Slim Array Processor," in Proceedings of the 10th International Parallel Processing Symposium, Honolulu, HI, April 15–19, 1996.
H.M. Chang, S. Ong, and M.H. Sunwoo, "A Linear Array Paral-lel Image Processor: Slim-ii," in Proceedings of the International Conference on Applications-Specific Systems, Architecture and Processors, Zurich, Switzerland, July 14–16, 1997.
D. Helman and J. J´aJ´a. "Efficient Image Processing Algorithms on the Scan Line Array Processor," IEEE Transaction on Pattern Analysis and Machine Intelligence, vol. 17, no. 1, 1995, pp. 17–56.
R.B. Yates, N.A. Thacker, S.J. Evans, S.N. Walker, and P.A. Ivey, "An Array Processor for General Purpose Digital Image Compression, " IEEE Journal of Solid-State Circuits, vol. 30, no. 3, 1995, pp. 244–249.
M. Schenkel, H. Weissman, I. Guyon, C. Nohl, D. Henderson, "Recognition-based Segmentation of On-line Hand-printed Words," Advances in Neural Information Processing System 5, Morgan Kaufmann, 1993, pp. 723–730, Denver.
L.M. Reyneri, "Unification of Neural and Wavelet Networks and Fuzzy Systems," IEEE Transactions on Neural Networks, vol. 10, no. 6, July 1999, pp. 801–818.
L.C. Jain and B. Lazzerini (Eds.), "High-Speed Recognition of Handwritten Amounts on Italian Checks," Knowledge-Based Intelligent Techniques in Character Recognition, Florida: CRC Press, 1999.
Adaptive Solutions, "CNAPS" data sheet and manuals.
F. Gregoretti, L.M. Reyneri, and C. Sanso´e, "An Intelligent Register File for Neural Processing Applications," in Proceedings of WDTA '98, Workshop on Design, Test and Applications, Dubrovnik, Croatia, June 1998, pp. 41–44.
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Gregoretti, F., Passerone, R., Reyneri, L.M. et al. A High Speed VLSI Architecture for Handwriting Recognition. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 28, 259–278 (2001). https://doi.org/10.1023/A:1011173726562
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DOI: https://doi.org/10.1023/A:1011173726562