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An Approach to the Specification and Verification of a Hardware Compilation Scheme

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Abstract

The use of Field Programmable Gate Arrays (FPGA) to produce custom hardware circuits rapidly using a completely software-based process is becoming increasingly widespread. Specialized Hardware Description Languages (HDL) are used to describe and develop the required circuits. In this paper, we advocate using an even more general purpose programming language, based on Occam, for the automatic compilation of high-level programs to low-level circuits. The parallel constructs of Occam can map directly to hardware as conveniently as to software, with potentially dramatic speed-up of highly parallel algorithms. We demonstrate that the compilation process can be verified using algebraic refinement laws, increasing the confidence in its correctness. Verification is particularly important in high-integrity systems where safety or security is paramount. A prototype compiler has also been produced very directly from the theorems using the logic programming language Prolog.

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Authors and Affiliations

  1. Centre for Applied Formal Methods, School of Computing, Information Systems and Mathematics, South Bank University, Borough Road, London, SE1 0AA, UK

    Jonathan P. Bowen

  2. International Institute for Software Technology, The United Nations University, PO Box 3058, Macau

    He Jifeng

Authors
  1. Jonathan P. Bowen
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  2. He Jifeng
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Bowen, J.P., Jifeng, H. An Approach to the Specification and Verification of a Hardware Compilation Scheme. The Journal of Supercomputing 19, 23–39 (2001). https://doi.org/10.1023/A:1011184310224

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