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New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters

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Abstract

Two alternative BIST schemes are proposed for structural testing of pipelined Analog-to-Digital Converters (ADC). They are oriented to fault detection in the converter stages rather than to measure the whole ADC electrical performance parameters. The operational principle of both strategies relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a simple DC stimuli set which is easily obtained, without strong precision requirements, by a resistive network. The main differences between both strategies relate to the way the output response is evaluated. In the BIST#1 scheme, analog and digital outputs are compared with reference levels generated with a reference D/A converter and a counter. In the BIST#2 strategy, only digital outputs are available and they are compared with fault-free values previously stored in an on-chip register. The new techniques are intended to be used in pipelined converters of an arbitrary number of conversion stages and with a digital self-correction mechanism.

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References

  1. K. Arabi, B. Kaminska, and J. Rzeszut, “A New Built-in Self-Test Approach for D/A and A/D Converters,” in Proc. Inter. Conf. on CAD, 1994, pp. 491-494.

  2. R. de Vries, T. Zwemstra, E.M. Bruls, and P.P.L. Regtien, “Built-in Self Test Methodology for A/D Converters,” in Proc. European Design and Test Conference, March 1997, pp. 353-358.

  3. M. Ehsanian, B. Kaminska, and K. Arabi, “A New On-Chip Digital BIST for Analog-to-Digital Converters,” Microelectronic Reliability, vol. 38,no. 3, pp. 409-420, 1998.

    Google Scholar 

  4. J. Goes, J. Franca, N. Paulino, J. Grilo, and G. Temes, High-Linearity Calibration of Low-Resolution D/A Converters,” in Proc. ISCAS, vol. 5, London 1994, pp. 345-348.

    Google Scholar 

  5. J. Goes, J.C. Vital, and J.E. Franca, “Systematic Design for Optimization of High-Speed Self-Calibrated Pipelined A/D Converters,” IEEE Trans. on Circuits and Systems-II, vol. 45,no. 12, pp. 1513-1526, Dec. 1998.

    Google Scholar 

  6. J. Huang, C. Ong, and K. Cheng, “A BIST Scheme for On-Chip ADC and DAC Testing,” in Proc. Design, Automation and Test in Europe Conference (DATE), Paris 2000, pp. 216-220.

  7. A.N. Karanicolas, H.S. Lee, and K.L. Bacrania, “A 15-b 1 Msample/s Digitally Self-Calibrated Pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28,no. 12, pp. 1207-1215, Dec. 1993.

    Google Scholar 

  8. S. Kwak, B. Song, and K. Bacrania, “A 15-b, 5-Msamples/s Low-Spurious CMOS ADC,” IEEE J. Solid-State Circuits, vol. 32,no. 12, pp. 1866-1875, Dec. 1997.

    Google Scholar 

  9. H.S. Lee, D.A. Hodges, and P.R. Gray, “A Self-Calibrating 15 Bit CMOS A/D Converter,” IEEE J. Solid-State Circuits, vol. SC-19,no. 6, pp. 813-819, Dec. 1984.

    Google Scholar 

  10. S. Lee and B. Song, “Digital-Domain Calibration of Multistep Analog-to-Digital Converters,” IEEE J. Solid-State Circuits, vol. 27,no. 12, pp. 1679-1688, Dec. 1992.

    Google Scholar 

  11. S.H. Lewis and P. Gray, “A Pipelined 5-Ms/s 9-bit A/D Converter,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 954-961, Dec. 1987.

  12. S.H. Lewis, R. Ramachadran, and W.M. Snelgrove, “Indirect Testing of Digital-Correction Circuits in A/D Converters with Redundancy,” IEEE Trans on Circ. and Syst.-II, vol. 42,no. 7, pp. 437-445, July 1995.

    Google Scholar 

  13. S.H. Lewis, H.S. Fetterman, G.F. Gross, Jr., R. Ramachandran, and T.R. Viswanathan, “A 10-b 20Msamples/s A/D Converter,” IEEE J. Solid-State Circuits, vol. 27,no. 3, pp. 351-358, March 1992.

    Google Scholar 

  14. Y.M. Lin, B. Kim, and P.R. Gray, “A 143-b 2.5 Mhz Self-Calibrated Pipelined A/D Converter in 3-μm CMOS,” IEEE J. Solid-State Circuits, vol. 26,no. 4, pp. 628-636, April 1991.

    Google Scholar 

  15. C. Mangelsdorff, S.H. Lee, M. Martin, H. Malik, T. Fukuda, and H. Matsumoto, “Design for Testability in Digitally-Corrected ADC's,” in Proc. Intern. Symp. on Solid-State Circuits, 1993, pp. 70-71.

  16. E.J. Peralías, A. Rueda, J.A. Prieto, and J.L. Huertas, “DFT & On-line Test of High Performance Data Converters,” in Proc. Intern. Test Conference, Oct. 1998, pp. 534-540.

  17. B. Razavi, Principles of Data Conversion System Design, IEEE Press, New York, NY, 1995.

    Google Scholar 

  18. S.K. Sunter and N. Nagi, “A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST,” in Proc. International Test Conference, 1997, pp. 389-395.

  19. M.F. Toner and G.W. Roberts, “A BIST Scheme for an SNR Test of a Sigma-Delta ADC,” in Proc. Int. Test Conf., 1993, pp. 805-814.

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Authors and Affiliations

  1. Instituto de Microelectrónica de Sevilla (IMSE-CNM), Universidad de Sevilla, Edificio CICA, c/Tarfia s/n, 41012-, Sevilla, Spain

    Eduardo J. Peralías, Adoración Rueda & José L. Huertas

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  1. Eduardo J. Peralías
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  2. Adoración Rueda
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  3. José L. Huertas
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Peralías, E.J., Rueda, A. & Huertas, J.L. New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters. Journal of Electronic Testing 17, 373–383 (2001). https://doi.org/10.1023/A:1012747017838

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