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Digital Window Comparator DfT Scheme for Mixed-Signal ICs

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Abstract

The possibility of using window comparators for on-chip and potentially also on-line response evaluation of analogue circuits is investigated. No additional analogue test inputs are required. The additional circuitry can be either realised by means of standard digital gates taken from an available library or by full custom designed gates. With only a few gates an observation window can be realized, tailored to the application needs. With this approach, the test overhead can be kept extremely low. Due to the low gate capacitance also the load on the observed nodes is very low. Simulation results for some examples show that 100% of all assumed layout-realistic faults could be detected.

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Authors and Affiliations

  1. Dipartimento di Elettrotecnica ed Elettronica, Politecnico di Bari, via Orabona 4, 70125, Bari, Italy

    Daniela De Venuto

  2. Automotive Products, Alcatel Microelectronics, Excelsiorlaan 44-46, 1930, Zaventem, Belgium

    Michael J. Ohletz

  3. DEIS, Università di Bologna, Viale Risorgimento 2, I-40126, Bologna, Italy

    Bruno Riccò

Authors
  1. Daniela De Venuto
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  2. Michael J. Ohletz
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  3. Bruno Riccò
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De Venuto, D., Ohletz, M.J. & Riccò, B. Digital Window Comparator DfT Scheme for Mixed-Signal ICs. Journal of Electronic Testing 18, 121–128 (2002). https://doi.org/10.1023/A:1014937424827

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  • DOI: https://doi.org/10.1023/A:1014937424827

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