Abstract
This paper presents a methodology to insert scan paths in a functional Register Transfer Level (RTL) specification of a design that can exploit existing functional paths between sequential elements in the original circuit for establishing scan chains. The primary objective for RTL scan insertion is to reduce the time taken for DFT, and thus reduce the time to market. Additionally, building scan chains at the functional RT-Level is expected to reduce the total area overhead introduced by full scan without compromising the fault coverage achieved. In addition, it often eliminates the delay associated with the additional multiplexer as a part of a conventional scan-cell in high performance designs. Experimental results presented in this paper demonstrate that the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.
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Huang, Y., Tsai, CC., Mukherjee, N. et al. Synthesis of Scan Chains for Netlist Descriptions at RT-Level. Journal of Electronic Testing 18, 189–201 (2002). https://doi.org/10.1023/A:1014949727553
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DOI: https://doi.org/10.1023/A:1014949727553