Abstract
This paper proposes a distributed two-rail checker architecture which is specifically targeted to self-checking bus-based systems. The architecture makes use of a single bus line to provide error indication. With respect to conventional two-rail checkers additional diagnosing capabilities are provided. The checker is totally-self-checking with respect to stuck-at faults. It features also good self-testing properties with respect to parametric faults, such as bridgings and delay faults.
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References
D.A. Anderson, “Design of Self-Checking Digital Network Using Coding Techniques,” Tech. Report R-527, CSL, Univ. of Illinois, IL, 1971.
D.A. Anderson and G. Metze, “Design of Totally Self-Checking Circuits for m-out-of-n Codes,” IEEE Transactions on Computers, vol. C-22, pp. 263–269, March 1973.
S. Kundu, E.S. Sogomonyan, M. Goessel, and S. Tarnick, “Self-Checking Comparator with One Periodic Output,” IEEE Transactions on Computers, vol. C-45, pp. 379–380, March 1996.
P. Lala, Self-Checking and Fault Tolerant Digital Design, San Mateo, CA: Academic Press, 2001.
C. Metra, M. Favalli, and B. Ricc´o, “Compact and Highly Testable Error Indicator for Self-Checking Circuits,” in IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, 1996, pp. 204–212.
C. Metra, M. Favalli, and B. Ricc´o, “Highly Testable and Compact Single Output Comparator,” in IEEE VLSI Test Symposium, 1997, pp. 210–215.
C. Metra, M. Favalli, and B. Ricc´o, “On-Line Testing and Diagnosis Scheme for Intermediate Voltage Values Affecting Bus Lines,” in IEEE Int. Workshop on Defect Based Testing, 2000, pp. 76–81.
C. Metra, M. Favalli, and B. Ricc´o, “Self-Checking Detection and Diagnosis for Transient, Delay and Crosstalk Faults Affecting Bus Lines,” IEEE Transaction on Computers, vol. C-49, no. 6, pp. 560–574, June 2000.
M. Nicolaidis, I. Jansch, and B. Courtois, “Strongly Code-Disjoint Checkers,” in Proc. of Int. Symp. Fault-Tolerant Comput, 1984, pp. 16–21.
M. Nicolaidis and Y. Zorian, “On-Line Testing for VLSI—A Compendium of Approaches,” J. of Electronic Testing: Theory and Application, vol. 12, pp. 7–20, 1998.
D. Pradhan (Ed.), Fault-Tolerant Computing: Theory and Techniques, Englewood Cliffs, NJ: Prentice-Hall, 1986.
R. Rodriguez-Montanes, E. Bruls, and J. Figueras, “Bridging Defects Resistance in the Metal Layer of a CMOS Process,” Journal-of-Electronic-Testing:-Theory-and-Applications, vol. 8, no. 1, pp. 35–46, 1996.
M. Sivaraman and A. Strojwas, A Unified Approach for Timing Verification and Delay Fault Testing, Dordrecht: Kluwer, 1998.
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Favalli, M., Metra, C. Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. Journal of Electronic Testing 18, 273–283 (2002). https://doi.org/10.1023/A:1015031121350
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DOI: https://doi.org/10.1023/A:1015031121350