Abstract
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the reseeding is performed on-the-fly by inverting the logic value of some of the bits of the next state of the Test Pattern Generator (TPG). The proposed reseeding technique is generic and can be applied to TPGs based on both Linear Feedback Shift Registers (LFSRs) and accumulators. An efficient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and allows to well exploiting the trade-off between hardware overhead and test length. Using experimental results we show that the proposed method compares favorably to the other already known techniques with respect to test length and the hardware implementation cost.
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References
M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, NewYork: Computer Science Press, 1990.
V. Agrawal, C. Kime, and K. Saluja, “A Tutorial on Built-In Self-Test Part 1: Principles,” IEEE Design & Test of Computers, pp. 73–82, March 1993.
V. Agrawal, C. Kime, and K. Saluja, “ATutorial on Built-In Self-Test Part 2: Applications,” IEEE Design & Test of Computers, pp. 69–77, June 1993.
M.F. AlShaibi and C.R. Kime, “MFBIST: A BIST Method for Random Pattern Resistant Circuits,” in Proc. of International Test Conference, 1996, pp. 176–185.
D. Bakalis, D. Nikolos, and X. Kavousianos, “Test Response Compaction by An Accumulator Behaving as a Multiple-Input Non-Linear Feedback Shift Register,” in Proc. of International Test Conference, 2000, pp. 804–811.
P.H. Bardell, W.H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudo-Random Techniques, New York: Johh Wiley & Sons, 1987.
K. Chakrabarty, B.T. Murray, and V. Iyengar, “Built-in Test Pattern Generation For High-Performance Circuits Using Twisted-Ring Counters,” in Proc. of 17th IEEE VLSI Test Symposium, 1999, pp. 22–27.
K. Chakrabarty and S. Swaminathan, “Built-in Testing of High-Performance Circuits Using Twisted-Ring Counters,” in Proc. of IEEE International Symposium on Circuits and Systems, 2000, pp. 72–75.
M. Chatterjee and D. Pradhan, “A Novel Pattern Generator for Near-Perfect Fault Coverage,” in Proc. of 13th IEEE VLSI Test Symposium, 1995, pp. 417–425.
S. Chiusano, P. Prinetto, and H.J. Wunderlich, “Non-Intrusive BIST for Systems-on-a-Chip,” in Proc. of International Test Conference, 2000, pp. 644–651.
S. Chiusano, S. Di Carlo, P. Prinetto, and H.J. Wunderlich, “On Applying the Set Covering Model to Reseeding,” in Proc. of Design, Automation & Test in Europe Conference, 2001, pp. 156–160.
C. Fagot, P. Girard, and C. Landrault, “On Using Machine Learning for Logic BIST,” in Proc. of International Test Conference, 1997, pp. 338–346.
C. Fagot, O. Gascuel, P. Girard, and C. Landrault, “On Calculating Efficient LFSR Seeds for Built-In SelfTest,” in Proc. of IEEE European Test Workshop, 1999, pp. 7–14.
S. Gupta, J. Rajski, and J. Tyszer, “Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns,” IEEE Trans. on Computers, vol. 45, no. 8, pp. 939–949, Aug. 1996.
S. Hellebrand, S. Tarnick, B. Courtois, and J. Rajski, “Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” in Proc. of International Test Conference, 1992, pp. 120–129.
S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” IEEE Trans. on Computers, vol. 44, no. 2, pp. 223–233, Feb. 1995.
L.R. Huang, J.Y. Jou, and S.Y. Kuo, “Gauss-Elimination-Based Generation of Multiple Seed-Polynomial Pairs for LFSR,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 9, pp. 1015–1024, Sep. 1997.
X. Kavousianos, D. Bakalis, and D. Nikolos, “A Novel Reseeding Technique for Accumulator-Based Test Pattern Generation,” in Proc. of 11th ACM Great Lakes Symposium on VLSI, 2001, pp. 7–12.
G. Kiefer and H. Wunderlich, “Using BIST Control for Pattern Generation,” in Proc. of International Test Conference, 1997, pp. 347–355.
B. Koenemann, “LFSR-Coded Test Patterns for Scan Design,” in Proc. of European Test Conference, 1991, pp. 237–242.
M. Lempel, S.K. Gupta, and M.A. Breuer, “Test Embedding with Discrete Logarithms,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 5, pp. 554–566, May 1995.
N. Mukherjee, M. Kassab, J. Rajski, and J. Tyszer, “Arithmetic Built-In Self-Test for High Level Synthesis,” in Proc. of 13th IEEE VLSI Test Symposium, 1995, pp. 132–139.
S.K. Mukund, E.J. McCluskey, and T.R.N. Rao, “An Apparatus for Pseudo-Deterministic Testing,” in Proc. of 13th IEEE VLSI Test Symposium, 1995, pp. 125–131.
F. Muradali, V.K. Agarwal, and B. Nadeau-Dostie, “A New Procedure for Weighted Random Built-In Self-Test,” in Proc. of International Test Conference, 1990, pp. 660–669.
I. Pomeranz and S.M. Reddy, “On Methods to Match a Test Pattern Generator to a Circuit-Under-Test,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 3, pp. 432–444, Sep. 1998.
J. Rajski and J. Tyszer, “Test Responses Compaction in Accumulators with Rotate Carry Adders,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 4, pp. 531–539, April 1993.
J. Rajski and J. Tyszer, “Accumulator-Based Compaction of Test Responses,” IEEE Trans. on Computers, vol. 42, no. 6, pp. 643–650, June 1993.
J. Rajski and J. Tyszer, Arithmetic Built-In Self-Test for Embedded Systems, Upper Saddle River, New Jersey: Prentice Hall PTR, 1998.
J. Savir and W.H. McAnney, “A Multiple Seed Linear Feedback Shift Register,” IEEE Trans. on Computers, vol. 41, no. 2, pp. 250–252, Feb. 1992.
A.P. Stroele, “Test Response Compaction Using Arithmetic Functions,” in Proc. of 14th IEEE VLSI Test Symposium, 1996, pp. 380–386.
A.P. Stroele, “Arithmetic Pattern Generators for Built-In Self-Test,” in Proc. of International Conference on Computer Design, 1996, pp. 131–134.
A.P. Stroele and F. Mayer, “Methods to Reduce Test Application Time for Accumulator-based Self-Test,” in Proc. of 15th IEEE VLSI Test Symposium, 1997, pp. 48–53.
A.P. Stroele and F. Mayer, “Test Length Reduction for Accumulator-based Self-Test,” in Proc. of International Symposium on Circuits and Systems, 1997, pp. 2705–2708.
A.P. Stroele, “BIST Pattern Generators Using Addition and Subtraction Operations,” Journal of Electronic Testing: Theory and Applications, vol. 11, no. 1, pp. 69–80, Aug. 1997.
A.P. Stroele, “Synthesis for Arithmetic Built-In Self-Test,” in Proc. of 18th IEEE VLSI Test Symposium, 2000, pp. 165–170.
N.A. Touba and E.J. McCluskey, “Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST,” in Proc. of International Test Conference, 1995, pp. 674–682.
S. Venkataraman, J. Rajski, S. Tarnick, and S. Hellebrand, “An Efficient BIST Scheme based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers”, in Proc. of International Conference on Computer-Aided Design, 1993, pp. 572–577.
J.A. Waicukauski, E. Lindenbloom, E.B. Eichelberger, and O.P. Forlenza, “A Method for Generating Weighted Random Patterns,” IBM Journal of Research and Development, vol. 33, no. 2, pp. 149–161, March 1989.
H.J. Wunderlich, “BIST for Systems-on-a-Chip,” Integration, The VLSI Journal, vol. 26, no. 1-2, pp. 55–78, Dec. 1998.
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Kalligeros, E., Kavousianos, X., Bakalis, D. et al. On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. Journal of Electronic Testing 18, 315–332 (2002). https://doi.org/10.1023/A:1015039323168
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DOI: https://doi.org/10.1023/A:1015039323168