Abstract
In this paper we describe an FPGA-based approach to speed-up fault injection campaigns for the evaluation of the fault-tolerance of VLSI circuits. Suitable techniques are proposed, allowing emulating the effects of faults and observing faulty behavior. The proposed approach combines the efficiency of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that significant speed-up figures can be achieved with respect to state-of-the-art simulation-based fault injection techniques.
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Civera, P., Macchiarulo, L., Rebaudengo, M. et al. An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. Journal of Electronic Testing 18, 261–271 (2002). https://doi.org/10.1023/A:1015079004512
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DOI: https://doi.org/10.1023/A:1015079004512