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Abstract

Several DSP algorithms need to remove high-frequency or impulsive noise while preserving edges, e.g., in speech and image processing applications: median filtering has been proved to be more effective for achieving this goal than other filtering techniques. Efficient architectural implementation for real-time applications involves a careful VLSI design, which takes into account modularity, regularity, adaptability, scalability, throughput, circuit complexity and fault tolerance.

Four new architectural approaches are presented and evaluated in this paper to deal with different application and implementation constraints. They are: the serial-input polarizing median filter, the floating median filter, the pipelined polarizing median filter and the pipelined sorting median filter. The 1st and the 2nd architectures are based on majority voting, while the 3rd and the 4th ones are based on sorting techniques. All of them are designed so as to exhibit high scalability and to be easily pipelined for higher working frequencies.

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References

  1. W. Pratt, Digital Image Processing, New York, USA: John Wiley & Son, 1978.

    Google Scholar 

  2. T.S. Huang (ed.), Two-Dimensional Digital Signal Processing II: Transforms and Median Filters, New York: Springer Verlag, 1981.

    Google Scholar 

  3. N.C. Gallagher and G.L. Wise, “A Theoretical Analysis of the Properties of Median Filters,” IEEE Transactions on Acoustic, Speech and Signal Processing, vol. ASSP-29, 1981, pp. 1136-1141.

    Article  Google Scholar 

  4. D.S. Richards, “VLSI Median Filters,” IEEE Transactions on Acoustic, Speed and Signal Processing, vol. 38,no. 1, Jan. 1990, pp. 145-153.

    Article  MathSciNet  Google Scholar 

  5. Proceedings of the 1992 IEEE International Symposium on Circuits and Systems, San Diego, CA, USA, May, 1992.

  6. Proceedings of the 1992 IEEE International Workshop on VLSI Signal Processing, Napa Valley, CA, USA, Oct. 1992.

  7. S.Y. Kung, VLSI Array Processors, Englewood Cliffs, NJ, USA: Prentice Hall, 1989.

    Google Scholar 

  8. L.E. Lucke and K.K. Parhi, “A New VLSI Architecture for Rank Order and Stack Filters,” in Proceedings of the IEEE International Symposium on Circuits and Systems, 1992.

  9. L.E. Lucke and K.K. Parhi, “Parallel Structures for Rank Order and Stack Filters,” in Proceedings of the IEEE International Conference on Acoustic, Speech and Signal Processing, 1992.

  10. M. Karaman, L. Onural, and A. Atalar, “Design and Implementation of a General Purpose Median Filter in VLSI,” in VLSI Signal Processing III, IEEE Press, 1988.

  11. P.D. Wendt, E.J. Coyle, and N.C. Gallager, “Stack Filters,” in IEEE Transactions on Signal Processing, 1986.

  12. G.R. Arce and P.J. Warter, “A Median Filter Architecture Suitable for VLSI Implementation,” in Proceedings of the 23rd Annual Allerton Conference of Communication Control Computing, Oct. 1984, pp. 172-181.

  13. A.L. Fisher, “Systolic Algorithms for Running Order Statistics in Signal and Image Processing,” Journal of Digital Systems, vol. 4,no. 2/3, 1982, pp. 251-264.

    Google Scholar 

  14. L.W. Chang and J.H. Lin, “A Bit-Level Systolic Array for Median Filter,” IEEE Transactions on Signal Processing, vol. 40,no. 8, 1992, pp. 2079-2083.

    Article  MathSciNet  Google Scholar 

  15. C.L. Lee and C.W. Jen, “Bit-Sliced Median Filter Design based on Majority Gate,” IEE Proceedings on Circuits, Devices and Systems, vol. 1391, 1992, pp. 63-71.

    Article  Google Scholar 

  16. E.H. Lu, J.Y. Lee, and Y. Yang, “VLSI Architecture for Median Filters with Linear Complexity,” TECNON '96, Proceedings on Digital Signal Processing Applications, vol. 1, 1996, pp. 358-362.

    Google Scholar 

  17. R. Roncella, R. Salemi, and P. Terreni, “70-MHz 2μm CMOS Bit-Level Systolic Array Median Filter,” IEEE Journal of Solid-State Circuits, vol. 28,no. 5, 1993, pp. 530-536.

    Article  Google Scholar 

  18. E. Ataman, V.K. Aatre, and K.M. Wong, “A Fast Method for Real-Time Median Filtering,” IEEE transactions on Acoustic, Speech and Signal Processing, vol. ASSP-28,no. 4, 1980, pp. 415-420.

    Article  Google Scholar 

  19. CMOS Macrocell Array Design Manual, SGS-Thomson Microelectronics, Italy, 1990.

  20. K. Hwang, Computer Arithmetic, New York, USA: John Wiley & Sons, 1979.

    Google Scholar 

  21. T.R.N. Rao, Error Coding for Arithmetic Processors, New York, USA: Academic Press, 1988.

    Google Scholar 

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Breveglieri, L., Piuri, V. Digital Median Filters. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 31, 191–206 (2002). https://doi.org/10.1023/A:1015487418553

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  • DOI: https://doi.org/10.1023/A:1015487418553

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