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Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

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Abstract

A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM built-in self-test (BIST) circuit that has diagnostic support to the external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio (size of original data to that of compressed data) is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the tree-based compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.

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References

  1. A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, and M. Lobetti-Bodorni, “A Programmable BIST Architecture for Clusters of Multiple-Port SRAMs, ” in Proc. Int. Test Conf. (ITC), 2000, pp. 557–566.

  2. T.J. Bergfeld, D. Niggemeyer, and E.M. Rudnick, “Diagnostic Testing of Embedded Memories Using BIST, ” in Proc. Design, Automation and Test in Europe (DATE), Paris, March 2000, pp. 305–309.

  3. B. Brown, J. Donaldson, B. Gage, and A. Joffe, “Hardware Compression Speeds on Bitmap Fail Display, ” in Proc. Int. Test Conf. (ITC), 1997, pp. 89–93.

  4. A. Chandra and K. Chakrabarty, “System-on-a-Chip Test-Data Compression and Decompression Architectures Based on Golomb Codes, ” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 3, pp. 355–368, March 2001.

    Google Scholar 

  5. M.F. Chang, W.K. Fuchs, and J.H. Patel, “Diagnosis and Repair of Memory with Coupling Faults, ” IEEE Transactions on Computers, vol. 38, no. 4, pp. 493–500, April 1989.

    Google Scholar 

  6. J.T. Chen, J. Rajski, J. Khare, O. Kebichi, and W. Maly, “Enabling Embedded Memory Diagnosis via Test Response Compression, ” in Proc. IEEE VLSI Test Symp. (VTS), Marina Del Rey, California, April 2001, pp. 292–298.

  7. A.L. Crouch, M. Mateja, T.L. McLaurin, J.C. Potter, and D. Tran, “The Testability Features of the 3rd Generation ColdFire Family of Microprocessors, ” in Proc. Int. Test Conf. (ITC), 1999, pp. 913–922.

  8. R. Dekker, F. Beenker, and L. Thijssen, “A Realistic Fault Model and Test Algorithm for Static Random Access Memories, ” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 6, pp. 567–572, June 1990.

    Google Scholar 

  9. D.A. Huffman, “A Method for the Construction of Minimum-Redundancy Codes, ” in Proc. IRE, vol. 40, pp. 1098–1101, Sept. 1952.

    Google Scholar 

  10. C. Hunter, “Integrated Diagnostics for Embedded Memory Built-in Self Test on PowerPC Devices, ” in Proc. IEEE Int. Conf. Computer Design (ICCD), 1997, pp. 549–554.

  11. S.S. Iyer and H.L. Kalter, “Embedded DRAM Technology: Opportunities and Challenges, ” IEEE Spectrum, pp. 56–64, April 1999.

  12. A. Jas and N.A. Touba, “TestVector Decompression via Cyclical Scan Chains and its Application toTesting Core-Based Designs, ” in Proc. Int. Test Conf. (ITC), 1998, pp. 458–464.

  13. D.A. Lelewer and D.S. Hirschberg, “Data Compression, ” ACM Computing Surveys, vol. 19, no. 3, pp. 261–296, Sept. 1987.

    Google Scholar 

  14. J.-F. Li, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, “March-Based RAM Diagnosis Algorithms for Stuck-at and Coupling Faults, ” in Proc. Int. Test Conf. (ITC), Baltmore, Oct. 2001, pp. 758–767.

  15. J.-F. Li, R.-S. Tzeng, and C.-W. Wu, “Using Syndrome Compression for Memory Built-in Self-Diagnosis, ” in Proc. Int. Symp. VLSI Technology, Systems, and Applications (VLSI-TSA), Hsinchu, April 2001, pp. 303–306.

  16. J.-F. Li and C.-W. Wu, “Memory Fault Diagnosis by Syndrome Compression, ” in Proc. Design, Automation and Test in Europe (DATE), Munich, March 2001, pp. 97–101.

  17. K.-J. Lin and C.-W. Wu, “Testing Content-Addressable Memories Using Functional Fault Models and March-Like Algorithms, ” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 5, pp. 577–588, May 2000.

    Google Scholar 

  18. J.M. Mulder, N.T. Quach, and M.J. Flynn, “An Area Model for On-Chip Memories and its Application, ” IEEE Journal of Solid-State Circuits, vol. 26, no. 2, pp. 98–106, Feb. 1991.

    Google Scholar 

  19. M. Rich, “A Method of Flexible Catch RAM Display for Memory Testing, ” in Proc. Int. Test Conf. (ITC), 1986, p. 222.

  20. L. Shen and B.F. Cockburn, “An Optimal March Test for Locating Faults in DRAMs, ” in Proc. IEEE Int.Workshop on Memory Testing, 1993, pp. 61–66.

  21. A.J. van de Goor, “Using March Tests to Test SRAMs, ” IEEE Design & Test of Computers, vol. 10, no. 1, pp. 8–14, March 1993.

    Google Scholar 

  22. C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, “A Built-in Self-Test and Self-Diagnosis Scheme for Embedded SRAM, ” in Proc. Ninth IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 45–50.

  23. C.-F. Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu, “Error Catch and Analysis for Semiconductor Memories using March Tests, ” in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), San Jose, Nov. 2000, pp. 468–471.

  24. C.-F. Wu, C.-T. Huang, and C.-W.Wu, “RAMSES:AFast Memory Fault Simulator, ” in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Albuquerque, Nov. 1999, pp. 165–173.

  25. C.-W. Wu, J.-F. Li, and C.-T. Huang, “Core-Based System-on-Chip Testing: Challenges and Opportunities, ” J. Chinese Institute of Electrical Engineering, vol. 8, no. 4, pp. 335–353, Nov. 2001.

    Google Scholar 

  26. T. Yabe, S. Miyano, K. Sato, M. Wada, R. Haga, O. Wada, M. Enkaku, T. Hojyo, K. Mimoto, M. Tazawa, T. Ohkubo, and K. Numata, “A Configurable DRAM Macro Design for 2112 Derivative Organizations to be Synthesized Using a Memory Generator, ” IEEE Journal of Solid-State Circuits, pp. 1752–1757, Nov. 1998.

  27. V.N. Yarmolik, Y.V. Klimets, A.J. van de Goor, and S.N. Demidenko, “RAM Diagnostic Tests, ” in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), San Jose, 1996, pp. 100–102.

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Authors and Affiliations

  1. Laboratory for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 30013, Taiwan, ROC

    Jin-Fu Li, Ruey-Shing Tzeng & Cheng-Wen Wu

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  1. Jin-Fu Li
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  2. Ruey-Shing Tzeng
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  3. Cheng-Wen Wu
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Li, JF., Tzeng, RS. & Wu, CW. Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test. Journal of Electronic Testing 18, 515–527 (2002). https://doi.org/10.1023/A:1016557927479

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