Abstract
A B‐ISDN national project in Korea has been carried out to develop a National Information Superhighway since 1992. An ATM switching system has been developed as one of the most important parts in the project, and has been tested in the National Information Superhighway testbed. In this paper, we develop a cell‐level/call‐level ATM switch simulator using cell‐level and call‐level input traffic models for evaluating the ATM switching system. The cell‐level simulator models various cell‐level switching functions such as priority control and multicast, and evaluates the cell‐level performance indices of the ATM switch in terms of cell delay, throughput, and cell loss probability. On the other hand, the call‐level simulator uses call‐level traffic models and evaluates the call blocking rate as a call‐level quality of service (QoS).
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
I.W. Causey and H.S. Kim, Comparison of buffer allocation schemes in ATM switches: Complete sharing, partial sharing, and dedicated allocation, in: ICC-94 (1994) pp. 1164–1168.
D.X. Chen and J.W. Mark, A buffer management scheme for the SCOQ switch under nonuniform traffic loading, in: IEEE INFOCOM-92 (1992) pp. 145–154.
J.S.-C. Chen and R. Guerin, Performance study of an input queueing packet switch with two priority classes, IEEE Transactions on Communications 39 (1991) 117–126.
F.M. Chiussi, J.G. Kneuer and V.P. Kumar, The ATLANTA architecture and chipset, in: ISS-97 (1997) pp. 43–52.
F.M. Chiussi, Ye Xia and V.P. Kumar, Performance of shared-memory switches under multicast bursty traffic, IEEE Journal on Selected Areas in Communications 15 (1997) 473–487.
A. Descloux, Stochastic models for ATM switching networks, IEEE Journal on Selected Areas in Communications 9 (1991) 450–457.
N. Endo, T. Kozaki, T. Ohuchi, H. Kuwahara and S. Gohara, Shared buffer memory switch for an ATM exchange, IEEE Transactions on Communications 41 (1993) 237–245.
J. Garcia-Haro, R.M. Sillue and J.M. Moreno, Description of a simulation environment to evaluate high performance ATM fast packet switches, in: HPN-94 (1994) pp. 421–436.
M.G. Hluchyj and M.J. Karol, Queueing in high-performance packet switching, IEEE Journal on Selected Areas in Communications 6 (1988) 1587–1597.
M.J. Karol, M.G. Hluchyj and S.P. Morgan, Input versus output queueing on a space-division packet switch, IEEE Transactions on Communications 35 (1987) 1347–1356.
H.S. Kim, I. Widjaja and A. Leon-Garcia, Performance of output-buffered Banyan networks with arbitrary buffer sizes, in: IEEE INFOCOM-91 (1991) pp. 701–710.
T. Kozaki, N. Endo, Y. Sakurai, O. Matsubara, M. Mizukami and K. Asano, 32 x 32 shared buffer type ATM switch VLSIs for B-ISDNs, IEEE Journal on Selected Areas in Communications 9 (1991) 1239–1247.
S. Kumar and D.P. Agrawal, A shared-buffer direct-access (SBDA) switch architecture for ATM-based networks, in: ICC-94 (1994) pp. 101–105.
S.-Q. Li, Nonuniform traffic analysis on a nonblocking space-division packet switch, IEEE Transactions on Communications 38 (1990) 1085–1096.
S.-Q. Li, Performance of a nonblocking space-division packet switch with correlated input traffic, IEEE Transactions on Communications 40 (1992) 97–108.
R.O. Onvural, Asynchronous Transfer Mode Networks: Performance Issues (Artech House, 1994).
Optimized engineering tools (OPNET) M version technical overview, MIL 3 Inc. (1994).
K.J. Schultz and P. Glenn Gulak, CAM-based single-chip shared buffer ATM switch, in: ICC-94 (1994) pp. 1190–1195.
Y. Shobatake, M. Motoyama, E. Shobatake, T. Kamitake, S. Shimizu, M. Noda and K. Sakaue, A one-chip scalable 8 x 8 ATM switch LSI employing shared buffer architecture, IEEE Journal on Selected Areas in Communications 9 (1991) 1248–1254.
E. Valdimarsson, General purpose simulation tool for analyzing switching systems, in: GLOBECOM-86 (1993) pp. 1358–1362.
H. Yamanaka, H. Saito, H. Kondoh, Y. Sasaki, H. Yamada, M. Tsuzuki, S. Nishio, H. Notani, A. Iwabu, M. Ishiwaki, S. Kohama, Y. Matsuda and K. Oshima, Scalable shared-buffering ATM switch with a versatile searchable queue, IEEE Journal on Selected Areas in Communications 15 (1997) 773–784.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Heo, J.W., Byun, S.H., Lee, J.Y. et al. Cell‐level/call‐level ATM switch simulator. Telecommunication Systems 14, 291–309 (2000). https://doi.org/10.1023/A:1019153803552
Issue Date:
DOI: https://doi.org/10.1023/A:1019153803552