Abstract
System-on-a-chip platform manufacturers are increasingly adding configurable features that provide power and performance flexibility, in order to increase a platform's applicability to a variety of embedded computing systems. We illustrate the energy benefits of combining the configurable features of voltage scaling and cache way shutdown in a single platform. We describe methods to assist a designer to tune such a platform to a particular software task and to particular energy optimization criteria.
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Albonesi, D. H. Selective CacheWays: On-Demand Cache Resource Allocation. Journal of Instruction Level Parallelism, May 2000.
Balasubramonian, R., D. Albonesi, A. Buyuktosunoglu, S. Dwarkadas. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures. Proceedings of Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2000.
Brooks, D., V. Tiwari, M.W. Martonosi. A Framework for Architectural-Level Power Analysis and Optimizations. Proceedings of Annual International Symposium on Computer Architecture, June 2000.
Burd, T. D., T. A. Pering, A. J. Stratakos, and R.W. Brodersen. A Dynamic Voltage Scaled Microprocessor System. IEEE International Solid-State Circuits Conference, November 2000.
Burger, D., and T. M. Austin.The SimpleScalarTool Set,Version 2.0.University of Wisconsin-Madison Computer Sciences Department Technical Report #1342, June 1997.
Edler, J., and M.D. Hill. Dinero IV Trace-Driven Uniprocessor Cache Simulator, http://www.cs.wisc.edu/~markhill/DineroIV.
Geppert, L., and T. S. Perry. Transmeta's Magic Show. IEEE Spectrum, vol. 37, no.5, pp. 26–33, May 2000.
Givargis, T. D., F. Vahid, and J. Henkel. System-Level Exploration for Pareto-Optimal Configurations in Parameterized System-on-a-Chip. Proceedings of the International Conference on Computer-Aided Design, Nov. 2001.
Halfhill, T. R. Transmeta Breaks x86 Low Power Barrier. Microprocessor Report, pp. 9–18, Feb. 2000.
Hong, I., M. Potkonjak, and M. B. Srivastava. On-Line Scheduling of Hard Real-TimeTasks on Variable Voltage Processor. International Conference on Computer-Aided Design, Nov. 1998.
Inoue, K., T. Ishihara, and K. Murakami. Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption. International Symposium on Low Power Electronics and Design, 1999.
Malik, A., B. Moyer, and D. Cermak. A Low Power Unified Cache Architecture Providing Power and Performance Flexibility. International Symposium on Low Power Electronics and Design, June 2000.
Nandi, A., R. Marculescu. System-Level Power/Performance Analysis for Embedded Systems Design. Design Automation Conference, pp. 599–604, 2001.
Rae, A., and S. Parameswaran.Voltage Reduction of Application-Specific Heterogeneous Multiprocessor Systems for Power Minimization. ASP-DAC, pp.147–152, 2000.
Pering, T., T. Burd, and R. Brodersen. The Simulation and Evaluation of Dynamic Voltage Scaling Algorithms. International Symposium on Low Power Electronics and Design, Aug. 1998.
Tiwari, V., S. Malik, and A. Wolfe. Power Analysis of Embedded Software: A First Step Toward Software Power Minimization. IEEE Transactions on VLSI Systems, vol. 2, no.4, pp. 437–445, 1994.
Veidenbaum, A.V., T. Weiyu, R. Gupta, A. Nicolau, and J. Xiaomei. Adapting Cache Line Size to Tas Behavior. International Conference on Supercomputing, June 1999.
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Givargis, T., Vahid, F. Tuning of Cache Ways and Voltage for Low-Energy Embedded System Platforms. Design Automation for Embedded Systems 7, 35–51 (2002). https://doi.org/10.1023/A:1019743330805
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DOI: https://doi.org/10.1023/A:1019743330805