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Partial Scan Testing on the Register-Transfer Level

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Abstract

This paper presents a methodology to insert scan paths in a design that is specified on the Register Transfer Level (RT-Level). The results indicate that selecting registers on this level guarantees a reduction in DFT design time and improvement of fault coverage, without incurring high hardware overhead.

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Authors and Affiliations

  1. Synopsys Inc., 700 E. Middlefield Way, Mountain View, CA, 94043

    Bruce S. Greene

  2. Electrical Engineering Department, Santa Clara University, 500 El Camino Real, Santaclara, CA, 95053

    Samiha Mourad

Authors
  1. Bruce S. Greene
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  2. Samiha Mourad
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Greene, B.S., Mourad, S. Partial Scan Testing on the Register-Transfer Level. Journal of Electronic Testing 18, 613–626 (2002). https://doi.org/10.1023/A:1020801123311

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