Abstract
Turbo codes achieve one of the highest coding gains known and should be the best candidates for error correction in high-speed communication systems. However, the standard implementation of their decoding algorithm suffers from a large latency and high power consumption making them improper for mobile interactive systems. To overcome this drawback, we carefully analyzed the Maximum A Posteriori algorithm, the key-building block of the decoder, and stated that memory accesses are the bottleneck. Therefore, we have systematically optimized the data transfer and storage. This paper presents the main results of this optimization, especially those concerning the memory organization and architecture.
Both for the input and the metrics values, a memory sub-layer is introduced such that temporal data locality can be maximally exploited. The architecture is defined to optimally allocate memory units and assign arrays, such that the number of accesses is drastically reduced. The combined optimizations reduce the latency by a factor 600 and the energy per bit by a factor 20, breaking definitely an important obstruction to the application of turbo codes in high-speed communication systems.
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Bougard, B., van der Perre, L., Maessen, F. et al. Memory Power Reduction for High-Speed Implementation of Turbo Codes. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 33, 307–316 (2003). https://doi.org/10.1023/A:1022132031284
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DOI: https://doi.org/10.1023/A:1022132031284