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Abstract

Turbo codes achieve one of the highest coding gains known and should be the best candidates for error correction in high-speed communication systems. However, the standard implementation of their decoding algorithm suffers from a large latency and high power consumption making them improper for mobile interactive systems. To overcome this drawback, we carefully analyzed the Maximum A Posteriori algorithm, the key-building block of the decoder, and stated that memory accesses are the bottleneck. Therefore, we have systematically optimized the data transfer and storage. This paper presents the main results of this optimization, especially those concerning the memory organization and architecture.

Both for the input and the metrics values, a memory sub-layer is introduced such that temporal data locality can be maximally exploited. The architecture is defined to optimally allocate memory units and assign arrays, such that the number of accesses is drastically reduced. The combined optimizations reduce the latency by a factor 600 and the energy per bit by a factor 20, breaking definitely an important obstruction to the application of turbo codes in high-speed communication systems.

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References

  1. C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon Limit Error Correcting Coding and Decoding: Turbo Codes," in IEEE International Conference on Communications (ICC'93), May 1993, vol. 2/3, pp. 1064-1071.

    Article  Google Scholar 

  2. L.R. Bahl, J. Cocke, F. Jelineck, and J. Raviv, "Optimal Decoding of Linear Codes for Minimizing Symbols Error Rate," in IEEE Transactions on Information Theory, March 1974, pp. 284-287.

  3. F. Maessen, L. van der Perre, F. Willems, M. Engels, F. Catthoor, and B. Gyselinckx, Memory Power Optimization for the Implementation of a High-Speed Turbo Decoder, SCVT Leuven, Belgium, 2000.

    Google Scholar 

  4. G. Masera et al., "VLSI Architectures for Turbo Codes," IEEE Transactions on VLSI Systems, vol. 7, no. 3, 1999, pp. 369-379.

    Article  Google Scholar 

  5. Z. Wang et al., "VLSI Implementation Issues of Turbo Decoder Design for Wireless Applications" In Proc. SiPS'99, Oct. 1999.

  6. C. Berrou, P. Adde, E. Angui, and S. Faudeil, "A Low Complexity Soft-OutputViterbi Decoder Architecture," in IEEE Proceedings of the paper.

  7. D. Garrett and M. Stan, "Low Power Architecture of the Soft-Output Viterbi Algorithm," ISLPED'98.

  8. S. Hong and W.E. Stark, "Design and Implementation of a Low Complexity VLSI Turbo Code Decoder Architecture for Low Energy MobileWireless Communications," Journal of VLSI Signal Processing Systems, vol. 24, 2000, pp. 43-57.

    Article  MATH  Google Scholar 

  9. F. Cathoor, S. Wuytack, E. de Greef, F. Balasa, L. Nachtergaele, and A. Vandecapelle, Custom Memory Management Methodology, Exploration of Memory Organization for Embedded Multimedia System Design, Kluwer Academic Publishers, 1988.

  10. C.E. Shannon, "A Mathematical Theory of Communication," The Bell System Technical Journal, July-Oct. 1948.

  11. J. Dielissen et al., "Power-Efficient Application-Specific VLIW Processor for Turbo Decoding," in ISSCC 2001, San Francisco, Feb. 2001. Memory Power Reduction 315

  12. C. Schurgers, F. Catthoor, and M. Engels, "Energy Efficient Transfer and Storage Organization for a MAP Turbo Decoder Module," in IEEE International Symosium on Low Power Design (ISLPED), San Diego, California, August 1999, pp. 76-81.

  13. O. Yuk-Hang Leung, C.-W. Yue, C. Tsui, and R.S. Cheng, "Reducing Power Consumption of Turbo Code Decoder Using Adaptive Iteration with Variable Supply Voltage," ISLPED'99.

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Bougard, B., van der Perre, L., Maessen, F. et al. Memory Power Reduction for High-Speed Implementation of Turbo Codes. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 33, 307–316 (2003). https://doi.org/10.1023/A:1022132031284

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  • DOI: https://doi.org/10.1023/A:1022132031284

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