Abstract
Constant-coefficient multipliers are used in many DSP cores. A new low-power constant multiplier, with detailed design procedure, is presented. By using canonical sign-digit (CSD) number system, and introducing new simplification techniques and identities, the multiplier features a new algorithm to reduce logic depth for the Wallace-tree implementation. The method also reduces area and complexity.
A generator written in C++ is used to generate technology-independent VHDL code of the constant multiplier for different input specifications. Synthesis results indicate the new design has smaller area and less power consumption while offering similar speed performance when compared with other multipliers.
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Pai, CY., Al-Khalili, A. & Lynch, W. Low-Power Constant-Coefficient Multiplier Generator. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 35, 187–194 (2003). https://doi.org/10.1023/A:1023604700591
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DOI: https://doi.org/10.1023/A:1023604700591