Abstract
This paper presents efficient techniques for mapping FIR filter computation circuits for PAM and QAM modulators onto systolic arrays. The exploitation of the inherent symmetry of these problem instances and the use of Look-Up Tables (L.U.T.) in conjunction with the use of systolic architectures, increases the performance while keeping the VLSI area minimal. Exploiting parallelism and pipelining enhances the throughput and results in linear expandability of the FIR filter with respect to the bit accuracy and to the stage count.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
A.V. Oppenheim and R.W. Schufer, Digital Signal Processing, Prentice Hall, 1975.
A. Chorevas, D. Reisis, and E. Metaxakis, “An Efficient Digital FIR Filter Design for 64 QAM,” in Proceedings of IEEE ICECS 1996, vol. 2, 1996, pp. 900–903.
S.Y. Kung, VLSI Array Processors, Prentice Hall, 1988.
K. Pohlmann, Principles of Digital Audio, 2nd edn., Howard Sams & Company, 1989.
L. Mintzer, “FIR Filters with the Xilinx FPGA,” FPGA '92 ACM/SIGDA Workshop on FPGAs, 1992, pp. 129–134.
F.T. Leighton, Parallel Algorithms and Architectures: Arrays-Trees-Hypercubes, Morgan Caufmann, 1992.
K. Pekmestzi, “Multiplexer-Based Array Multipliers,” IEEE Trans. on Computers, vol. 48, no. 1, 1999, pp. 15–23.
V. Oklabdzija and D. Villeger, “Improving Multiplier Design by Using Improved Comlumn Compression Tree and Optimized Final Adder in CMOS Technology,” IEEE Trans. on VLSI Systems, vol. 3, no. 2, 1995, pp. 292–301.
B. Cherkauer and E. Friedman, “AHybrid Radix-4/Radix-8 Low Power Signed Multiplier Architecture,” IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 44, no. 8, 1997, pp. 656–659.
H. Makino, Y. Nakase, H. Suzuki, H. Morinaka, H. Shinohara, and K. Mashino, “An 8.8-ns 54 × 54-Bit Multiplier with High Speed Redundant Binary Architecture,” IEEE Journal of Solid-State Circuits, vol. 31, no. 6, 1996, pp. 773–783.
H. Samueli, “An Improved Search Algorithm for the Design of Multiplierless FIR Filters With Power-of-two Coefficients,” IEEE Trans. Circuits Syst., vol. 36, no. 7, 1989, pp. 1044–1047.
A. Dempster and M. Macleod, “Constant Integer Multiplication Using Minimum Adders,” IEE Proc. Circuits Devices Syst., vol. 141, no. 5, 1994, pp. 407–413.
A. Dempster and M. Macleod, “General Algorithms for Reduced-Adder Integer Multiplier Design,” Electronics Letters, vol. 31, no. 21, 1995, pp. 1800–1802.
D. Li, “Minimum Number of Adders for Implementing a Multiplier and its Application to the Design of Multiplierless Digital Filters,” IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 42, no. 7, 1995, pp. 453–460.
K. Khoo, A. Kwentus, and A. Willson, “A Programmable FIR Digital Filter Using CSD Coefficients,” IEEE Journal of Solid-State Circuits, vol. 31, no. 6, 1996, pp. 869–874.
H. Lee, C. Jen, and C. Liu, “On the Design Automation of the Memory-based VLSI Architectures for FIR Filters,” IEEE Trans. Consumer Electron., vol. 39, no. 3, 1993, pp. 619–629.
A. Dempster and M. Macleod, “Use of Minimum Adder Multiplier Blocks in FIR Digital Filters,” IEEE Trans. Circuits Syst. II, vol. 42, no. 9, 1995, pp. 569–577.
T. Chang and C. Jen, “Hardware-Efficient Implementations for Discrete Function Transforms Using LUT Based FPGAs,” IEE Proceedings-Computers and Digital Techniques, vol. 146, no. 6, 1999, pp. 309-315.
J. Guo, “Efficient Parallel Adder Based Design for One-Dimensional Discrete Cosine Transform,” IEE Proceedings-Circuits Devices and Systems, vol. 147, no. 5, 2000, pp. 276–282.
Y. Tsunekawa, M. Iwawaki, and M. Miura, “A Low Power Dissipation Architecture of High-Performance Multiprocessor for State-Space Digital Filters Using Block-State Realization,” Electronics and Communications in Japan, Part III-Fundamental Electronic Science, vol. 83, no. 10, 2000, pp. 56–66.
R. Babic and B. Jarc, “The Modified Distributed Arithmetic Structure for the Basic and the Cascade Digital Filters Realization,” Informacije MIDEM Journal of Microelectronics Electronic Components and Materials, vol. 29, no. 3, 1999, pp. 136-142.
J.D. Ullman, Computational Aspects of VLSI, Computer Science Press, 1984.
K. Hwang, Computer Arithmetic (Principles, Architecture, and Design), John Wiley & Sons, 1979.
K. Chapman, “Constant Coefficient Multipliers for the XC400E,” XILINX Corp. Application Note XAPP 054, December 1996.
ALTERA, “Designing Multipliers in FLEX 8000 Devices,” Application Brief 127, May 1994.
J. Proakis, Digital Communications, McGraw-Hill, 1995.
D. Divsalar, M. Simon, and J. Yuen, “Trellis Coding with Asymmetric Modulations,” IEEE Trans. on Communications, vol. 35, no. 2, 1987, pp. 130–141.
A. Chorevas and D. Reisis, “Efficient and Expandable Interpolating FIR Filter Design and Implementation,” in Proceedings of the 3rd IMACS/IEEE CSCC, Athens, 1999, pp. 6791–6795.
N.Weste and K. Eshraghiam, Principles of CMOS VLSI Design, 2nd edn., Addison-Wesley, 1994.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Chorevas, A., Reisis, D. Efficient Systolic Array Mapping of FIR Filters Used in PAM-QAM Modulators. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 35, 179–186 (2003). https://doi.org/10.1023/A:1023652615612
Published:
Issue Date:
DOI: https://doi.org/10.1023/A:1023652615612