Abstract
This paper describes an architecture for controlling multiple IEEE 1149.1 compliant TAP controllers on a single digital system chip. The key feature of this architecture is the compatibility with the IEEE 1149.1 standard, and existing debugger software. Results are presented, obtained from an experiment, in which the proposed architecture is mapped on an FPGA to control multiple existing designs with TAP controllers.
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References
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Vermeulen, B., Waayers, T. & Bakker, S. Multi-TAP Controller Architecture for Digital System Chips. Journal of Electronic Testing 19, 417–424 (2003). https://doi.org/10.1023/A:1024691909923
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DOI: https://doi.org/10.1023/A:1024691909923