Abstract
This paper proposes the Cross-Parity check as a method for an on-line detection of multiple bit-errors in registers or register files of microprocessors. Transient or ‘soft’ errors caused by radiation as single event upsets (SEUs) or electromagnetic coupling are in the focus of this work. Especially for register files or register groups, an easy implementable error correction method is proposed, which can be implemented by software routines or additional hardware. The method is based on the logical interpretation of Cross-Parity vectors.
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M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital System Testing and Testable Design, New York: IEEE Press, 1990.
D.H. Allen et al., “Custom Circuit Design as a Driver of Microprocessor Performance,” IBM J. Res. Develop., vol. 44, no. 6, pp. 799-822, 2000.
J.M. Berger, “A Note on Error Detecting Codes for Asymmetric Channels,” Information and Control, vol. 4, pp. 68-73, 1961.
S. Buchner et al., “Comparison of Error Rates in Combinational and Sequential Logic,” IEEE Trans. on Nuclear Science, vol. 44, no. 6, pp. 2209-2216, 1997.
J.A. Clark and D.K. Pradhan, “Fault Injection: A Method for Validating Computer-System Dependability,” IEEE Computer, vol. 28, no. 6, pp. 47-56, 1995.
R.K. Gupta and Y. Zorian, “Introducing Core-Based System Design,” IEEE Design & Test of Computers, pp. 15-25, Oct.-Dec. 1997.
IEEE Computer Society, “IEEE Standard Test Access Port and Boundary-Scan Architecture-IEEE Std. 1149.1-1990,” IEEE, New York, 1990.
P.K. Lala, Self-Checking and Fault-Tolerant Digital Design, Morgan Kaufmann Publishers-Academic Press, July 2000.
K.W. Li, J.R. Armstrong, and J.G. Tront, “AnHDLSimulation of the Effects of Single Event Upsets On Microprocessor Program Flow,” IEEE Trans. on Nuclear Science, vol. NS-31, no. 6, 1984.
P.C. Li and T.K. Young, “Electromigration, The Time Bomb in Deep-submicron ICs,” IEEE Spectrum, vol. 33, no. 9, pp. 75-78, Sept. 1996.
C. Metra, M. Favalli, and B. Ricco, “Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines,” IEEE Trans. on Computers, vol. 49, no. 6, pp. 560-574, 2000.
R.H. Minero, A.J. Anello, R.G. Furey, and L.R. Palounek, “Checking by Pseudoduplication,” US Patent 3660646,GO6F 11/00, 1972.
M. Nicolaidis, “Online Testing for VLSI, State of the Art and Trends,” Integration the VLSI Journal, no. 28, pp. 197-209, 1998.
M. Pflanz, On-line Error Detection and Fast Recovery Techniques for Dependable Embedded Processors, Lecture Notes of Computer Sciences (LNCS), Springer, No. 2270, Feb. 2002, ISBN 3-540-43318-X.
M. Pflanz, K. Walther, and H.T. Vierhaus, “On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity,” in Proc. Int. On-line Test Workshop (IOLTW’01), 2001.
M. Rimen and J. Ohlson, “A Study of the Error Behavior of a 32-bit RISC Subjected to Simulated Transient Fault Injection,” in Proc. of the Int. Test Conference, Baltimore, USA, 1992, pp. 696-704.
N. Seifert et al., “Frequency Dependence of Soft Error Rates for Sub-Micron CMOS Technologies,” Proc. IEDM, 2001, pp. 323-326.
F.F. Sellers, M.J. Hsiao, and L.W. Bernson, Error Detecting Logic for Digital Computers, New York: McGraw-Hill Book Company, 1968.
S.B.Wicker and V.K. Bhargava, Reed-Solomon Codes and their Applications, IEEE Press.
N.T. Wing and E. Glen, “Self Checking Arithmetic Unit,” US Patent 4314350, GO6F 11/14.
Y. Zorian, E.J. Marinissen, and S. Dey, “Testing Embedded-Core Based System Chips,” Proc. ITC, 1998, pp. 130-143.
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Pflanz, M., Walther, K., Galke, C. et al. On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check. Journal of Electronic Testing 19, 501–510 (2003). https://doi.org/10.1023/A:1025165712071
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DOI: https://doi.org/10.1023/A:1025165712071