Abstract
Recent works1 show that delays introduced in the issue and bypass logic will become critical for wide issue superscalar processors. One of the proposed solutions is clustering the processor core. Clustered architectures benefit from a less complex partitioned processor core and thus, incur in less critical delays. In this paper, we propose a dynamic instruction steering logic for these clustered architectures that decides at decode time the cluster where each instruction is executed. The performance of clustered architectures depends on the inter-cluster communication overhead and the workload balance. We present a scheme that uses runtime information to optimize the trade-off between these figures. The evaluation shows that this scheme can achieve an average speed-up of 35% over a conventional 8-way issue (4 int + 4 fp) machine and that it outperforms other previous proposals, either static or dynamic.
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Canal, R., Parcerisa, JM. & González, A. Dynamic Code Partitioning for Clustered Architectures. International Journal of Parallel Programming 29, 59–79 (2001). https://doi.org/10.1023/A:1026483904675
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DOI: https://doi.org/10.1023/A:1026483904675