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A Reconfigurable Logic-Based Processor for the SCAN Image and Video Encryption Algorithm

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Abstract

This paper presents a detailed architecture and a reconfigurable logic based hardware design of the SCAN algorithm. This architecture can be used to encrypt high resolution images in real-time. Although the SCAN algorithm is a block cipher algorithm with arbitrarily large blocks, the present design is for 64×64 pixel blocks in order to provide real-time image encryption throughput. The architecture was initially targeted at the Xilinx XCV-1000 FPGA, for which design and performance results are presented in the paper.

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Kachris, C., Bourbakis, N. & Dollas, A. A Reconfigurable Logic-Based Processor for the SCAN Image and Video Encryption Algorithm. International Journal of Parallel Programming 31, 489–506 (2003). https://doi.org/10.1023/B:IJPP.0000004512.53221.ff

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  • DOI: https://doi.org/10.1023/B:IJPP.0000004512.53221.ff

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