Abstract
Application-specific integrated circuits (ASICs) and high-performance processors such as Itanium and Compaq Alpha use a total of almost 75% of chip real estate for accommodating various types of embedded (or on-chip) memories. Although most of these embedded memories are single-port static (and in relatively few cases, dynamic) RAMs today, the high demand for bandwidth in digital television, fast signal processing, and high-speed networking applications will also fuel the need for on-chip multiport memories in the foreseeable future. The reliability of a complex VLSI chip will depend largely on the reliability of these embedded memory blocks. With device dimensions moving rapidly toward the ultimate physical limits of device scaling, which is in the regime of feature sizes of 50 nm or so, a host of complex failure modes is expected to occur in memory circuits. This tutorial underlines the need for appropriate testing and reliability techniques for the present to the next generation of embedded RAMs. Topics covered include: reliability and quality testing, fault modeling, advanced built-in self-test (BIST), built-in self-diagnosis (BISD), and built-in self-repair (BISR) techniques for high-bandwidth embedded RAMs.
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References
R.D. Adams and E.S. Cooley, “Analysis of a Deceptive, Destructive Read Memory Fault Model and Recommended Testing,” IEEE North Atlantic Test Workshop, 1996.
R.D. Adams and E.S. Cooley, “False Writethrough and Unrestored Write Electrical Level Fault Models for SRAMs,” in Proc. Intl. Workshop on Memory Technology, Design and Testing, 1997, pp. 27-32.
L. Adams et al., “A Verified Proton-Induced Latchup in Space,” IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1804-1808, 1992.
A.A. Amin et al., “New Fault Models and Efficient BIST Algorithms for Dual-Port Memories,” IEEE Trans. CAD/ICAS, vol. 16, no. 9, pp. 987-1000, 1997.
P.P. Apte and K.C. Saraswat, “Correlation of Trap Generation to Charge-To-Breakdown (Q bd): A Physical-Damage Model of Dielectric Breakdown,” IEEE Trans. Electron Devices, vol. 41, no. 9, pp. 1595-1602, 1994.
C.L. Axness et al., “Mechanisms Leading to Single-Event Upset,” IEEE Trans. Nucl. Sci., vol. 33, no. 6, pp. 1577-1580, 1986.
T. Blalock and R.C. Jaeger, “A High-Speed Sensing Scheme for 1T Dynamic RAMs Utilizing the Clamped Bit-Line Sense Amplifier,” IEEE J. Solid State Circuits, vol. 27, no. 4, pp. 618-625, 1992.
T. Blalock and R.C. Jaeger, “A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier,” IEEE J. Solid State Circuits, vol. 26, no. 4, pp. 542-548, 1991.
V. Castro Alves et al., “Built-In Self-Test for Multiport RAMs,” in Proc. IEEE International Conf. on Computer Aided Design, (ICCAD) Santa Clara, USA, 1991, pp. 248-251.
K. Chakraborty, “BISRAMGEN: A Silicon Compiler for Built-In Self-Repairable Random-Access Memories,” Ph.D. thesis, The University of Michigan, Ann Arbor, 1997.
K. Chakraborty and P. Mazumder, “Technology and Layout-Related Testing of Static Random-Access Memories,” J. Electron. Test. Theory Appl., Special Issue on Memory Testing (JETTA), vol. 5, no. 4, pp. 347-365, 1994.
K. Chakraborty and P. Mazumder, “A Programmable Boundary Scan Technique for Board-Level, Parallel Functional Duplex March Testing of Word-Oriented Multiport Static RAM's,” in Proc. Eur. Des. Test Conf., Paris, France, March 1997, pp. 330-334.
K. Chakraborty and P. Mazumder, “New March Tests for Multiport RAM Devices,” Journal of Electronic Testing: Theory and Applications, vol. 16, pp. 389-395, 2000.
K. Chakraborty and P. Mazumder, Fault-Tolerance and Reliability Techniques for High-Density Random-Access Memories, Upper Saddle River, NJ: Prentice Hall, 2002.
K. Chakraborty et al., “A Physical Design Tool for Built-In Self-Repairable Static RAMs,” in Proc. Des. Automat. Test Eur. (DATE), 1999, pp. 714-718.
K. Chakraborty et al., “A Physical Design Tool for Built-In Self-Repairable RAMs,” IEEE Trans. VLSI Systems, vol. 9, no. 2, pp. 352-364, 2001.
T.Y.J. Chang et al., “Experimental Results for I DDQ and VLV Testing,” in Proc. 16th IEEE VLSI Test Symp., 1998, pp. 118-123.
T. Chen and G. Sunada, “Design of a Self-Testing and Self-Repairing Structure for Highly Hierarchical Ultra-Large Capacity Memory Chips,” IEEE Trans. VLSI Syst., vol. 1, no. 2, pp. 88-97, 1993.
J.T. Chen et al., “Test Response Compression and Bitmap Encoding for Embedded Memories in Manufacturing Process Monitoring,” in Proc. IEEE Int. Test Conf., 2001a, pp. 258-267.
J.T. Chen et al., “Enabling Embedded Memory Diagnosis via Test Response Compression,” in Rec. 16th VLSI Test Symp., 2001b.
A.L. Crouch, DFT for Digital ICs and Embedded Core Systems, Upper Saddle River, NJ: Prentice Hall, 1999.
J.H. De Jonge and A.J. Smeulders, “Moving Inversions Test Pattern is Thorough, yet Speedy,” Computer Design, pp. 169-173, May 1976.
R. Dekker, “Fault Modeling and Self-Test of Static Random Access Memories,” TUD rep. 1-68340-28(1987)25, Department of Electrical Engineering, Delft University of Technology, Delft, The Netherlands, 1987.
R. Dekker et al., “Fault Modeling and Test Algorithm Development for Static Random Access Memories,” in Proc. IEEE Int. Test Conf., 1988, pp. 343-352.
R. Dekker et al., “A Realistic Self-Test Machine for Word-Oriented Static Random-Access Memories,” in Proc. IEEE Int. Test. Conf., 1988, pp. 353-361.
R. Dekker et al., “Realistic Built-In Self-Test for Static RAMs,” IEEE Des. and Test Comput., vol. 6, no. 1, pp. 26-34, 1989.
R. Dekker et al., “A Realistic Fault Modeling and Test Algorithms for Static Random Access Memories,” IEEE Trans. Comput., vol. C-9, no. 6, pp. 567-572, 1990.
P.E. Dodd, “Basic Mechanisms for Single-Event Effects,” in 36th Annual IEEE Int. Nucl. and Space Radiat. Effects Conf. (NSREC) Short Course, 1999.
D.J. Dumin et al., “A Model Relating Wearout to Breakdown in Thin Oxides,” IEEE Trans. Electron Devices, vol. 41, no. 9, pp. 1570-1580, 1994.
A.E. Gattiker and W. Maly, “Current Signatures,” in Proc. 14th IEEE VLSI Test Symp., 1996, pp. 112-117.
S. Hamdioui, “Fault Models and Tests for Multiport Memories,” Masters Thesis, Delft Univ. Tech, Netherlands, 1997.
H. Hao and E.J. McCluskey, “Very Low Voltage Testing for Weak CMOS Logic ICs,” in Proc. IEEE Int. Test Conf., 1993, pp. 275-284.
C.F. Hawkins and J.M. Soden, “Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs,” in Proc. IEEE Int. Test Conf., 1986, pp. 443-451.
B. Johlander et al., “Ground Verification of In-Orbit Anomalies in the Double Probe Electric Field Experiment on Freja,” IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2767-2771, 1996.
A.H. Johnston, “The Influence of VLSI Technology Evolution on Radiation-Induced Latchup in Space Systems,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 505-521, 1996.
A. Keshavarzi et al., “Intrinsic Leakage in Deep Submicron CMOS ICs-Measurement-Based Test Solutions,” IEEE Trans. VLSI Syst., vol. 8, no. 6, pp. 717-723, 2000.
J. Khare et al., “SRAM-Based Extraction of Defect Characteristics,” in Prof. Int. Conf. Microelectron. Test Struct., 1994, pp. 98-107.
I. Kim et al., “Built-In Self-Repair for Embedded High-Density SRAM,” in Proc. IEEE Int. Test Conf., 1998, pp. 1112-1119.
H.-C. Kim et al., “A BISR (Built-In Self-Repair) Circuit for Embedded Memory with Multiple Redundancies,” in Int. Conf. on VLSI and CAD (ICVC), 1999, pp. 602-605.
M. Kimura, “Field and Temperature Acceleration Model for Time-Dependent Dielectric Breakdown,” IEEE Trans. Electron Devices, vol. 46, no. 1, pp. 220-229, 1999.
W.A.Kolasinski et al., “Simulation of Cosmic-Ray Induced Soft Errors and Latchup in Integrated-Circuit Computer Memories,” IEEE Trans. Nucl. Sci., vol. 26, no. 6, pp. 5087-5091, 1979.
J. Liu et al., “Dynamic Power Supply Current Testing of CMOS SRAMs,” J. Electron. Test. Theory Appl. (JETTA), vol. 16, pp. 499-511, 2000.
S.-K. Lu and C.-H. Hsu, “Built-In Self-Repair for DividedWord Line Memory,” in Proc. Int. Symp. Circuits and Syst., ISCAS, vol. 4, pp. 13-16, 2001.
W. Maly, “Modeling of Lithography-Related Yield Losses for CAD of VLSI Circuits,” IEEE Trans. CAD/ICAS, vol. 4, no. 3, pp. 166-177, 1985.
W. Maly and S. Naik, “Process Monitoring Oriented Testing,” in Proc. IEEE Int. Test Conf., 1989, pp. 527-532.
W. Maly et al., “Yield Diagnosis through Interpretation of Tester Data,” in Proc. IEEE Int. Test Conf., 1987, pp. 10-20.
P. Maxwell and P. O'Neill, “Current Ratios:ASelf-ScalingTechnique for Production I DDQ Testing,” in Proc. IEEE Int. Test Conf., 2000, pp. 1148-1156.
P. Mazumder and K. Chakraborty, Testing and Testable Design of High-Density Random-Access Memories, Kluwer Academic Publishers, 1996.
P. Mazumder and J.S. Yih, “A Novel Built-In Self-Repair Approach to VLSI Memory Yield Enhancement,” in Proc. IEEE Int. Test Conf., 1990, pp. 833-841.
R.F.M. Meershoek et al., “Functional and I DDQ Testing on a Static RAM,” in Proc. IEEE Int. Test Conf., 1990, pp. 929-937.
B. Nadeau-Dostie et al., “Serial Interfacing for Embedded-Memory Testing,” IEEE Des. and Test Comput., pp. 52-63, 1990.
S. Naik et al., “Failure Analysis of High-Density CMOS SRAMs Using Realistic Defect Modeling and I DDQ Testing,” IEEE Des. and Test Comput., pp. 13-23, 1993.
D.K. Nichols et al., “Discovery of Heavy-Ion-Induced Latchup in CMOS/Epi Devices,” IEEE Trans. Nucl. Sci., vol. 33, no. 6, p. 1696, 1986.
D.K. Nichols et al., “An Observation of Proton-Induced Latchup,” IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1654-1656, 1992.
M. Nicolaidis et al., “Testing Complex Couplings in Multiport Memories,” IEEE Trans. VLSI Syst., vol. 3, no. 1, pp. 59-71, 1995.
T. Ohsawa et al., “A 60 ns 4M CMOS DRAM with Built-In Self-Test Function,” IEEE J. Solid State Circuits, vol. 22, no. 5, pp. 663-667, 1987.
T.R. Oldham et al., “Total Dose Failure in Advanced Electronics from Single Ions,” IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1820-1830, 1993.
C. Pyron et al., “DFT Advances in Motorola's MPC7400, a PowerPC Microprocessor,” in Proc. IEEE Int. Test Conf., 1999, pp. 137-146.
V. Ratford, “Self-Repair Boosts Memory SoC Yields,” EE Design, Sept. 5, 2001.
E. Rosenbaum, and L.F. Register, “Mechanism of Stress-Induced Leakage Current in MOS Capacitors,” IEEE Trans. Electron Devices, vol. 44, no. 2, pp. 317-323, 1997.
K.K. Saluja and K. Kinoshita, “Test Pattern Generation for API Faults in RAM,” IEEE Trans. Comput., vol. C-34, no. 3, 1985, pp. 284-287.
K. Sawada et al., “Built-In Self-Repair Circuit for High-Density ASMIC,” in Proc. Custom Int. Circuits Conf. (CICC), 1989, pp. 26.1.1-26.1.2.
I. Schanstra et al., “Semiconductor Manufacturing Process Monitoring Using Built-In Self-Test for Embedded Memories,” in Proc. IEEE Int. Test Conf., 1998, pp. 872-881.
E. Seevinck et al., “Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAMs,” IEEE J. Solid State Circuits, vol. 26, no. 4, pp. 525-536, 1991.
J.P. Shen et al., “Inductive Fault Analysis of CMOS Integrated Circuits,” IEEE Des. and Test Comput., pp. 13-26, 1985.
J.M. Soden et al., “CMOS IC Stuck-Open Fault Electrical Effects and Design Considerations,” in Proc. Int. Test Conf., 1989, pp. 423-430
S. Su and R.Z. Makki, “Testing of Static Random-Access Memories by Monitoring Dynamic Power Supply Current,” J. Electron. Test. Theory Appl. (JETTA), vol. 3, pp. 265-278, 1992.
D.S. Suk and S.M. Reddy, “Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories,” IEEE Trans. Comput., vol. C-29, no. 6, pp. 419-429, 1980.
G.M. Swift et al., “A New Class of Single Event Hard Errors,” IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2043-2048, 1994.
T. Takeshima et al., “A 55 ns 16-Mb DRAM with Built-In Self-Test Function Using Microprogram ROM,” IEEE J. Solid State Circuits, vol. 25, no. 4, pp. 903-909, 1990.
C. Thibeault, “Detection and Location of Faults and Defects Using Digital Signal Processing,” in Proc. 13th IEEE VLSI Test Symp., 1995, pp. 262-267.
C. Thibeault, “Increasing Current Testing Resolution,” in Proc. IEEE Int. Symp. Defect and Fault Toler. VLSI Syst., 1998, pp. 126-134.
C. Thibeault, “On the Comparison of I DDQ and I DDQ Testing,” in Proc. 17th IEEE VLSI Test Symp., 1999, pp. 143-150.
I.B.S. Tlili and A.J. van de Goor, “Disturb Neighborhood Pattern Sensitive Fault,” in Proc. 15th IEEE VLSI Test Symp., 1997, pp. 37-45.
R. Treuer and V.K. Agarwal, “Built-In Self-Diagnosis for Repairable Embedded RAMs,” IEEE Des. and Test Comput., pp. 24-33, 1993.
C.-W. Tseng et al., “Cold Delay Defect Screening,” in Proc. 18th IEEE VLSI Test Symp., 2000, pp. 183-188.
C.-W. Tseng et al., “MINVDD Testing for Weak CMOS ICs,” in Proc. 19th IEEE VLSI Test Symp., 2001, pp. 339-344.
J.P. Uyemara, Fundamentals of MOS Digital Integrated Circuits, Addison-Wesley, MA, 1988.
A.J. van de Goor, Testing Semiconductor Memories-Theory and Practice, UK: Wiley, Chichester, 1991.
H.T. Weaver et al., “RAM Cell Recovery Mechanisms following High-Energy Ion Strike,” IEEE Electron Device Lett., vol. 8, no. 1, pp. 7-9, 1987.
T. Williams et al., “I DDQ Test: Sensitivity Analysis of Scaling,” in Proc. Intl. Test Conf., 1996, pp. 786-792.
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Chakraborty, K. Testing and Reliability Techniques for High-Bandwidth Embedded RAMs. Journal of Electronic Testing 20, 89–108 (2004). https://doi.org/10.1023/B:JETT.0000009316.94309.66
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DOI: https://doi.org/10.1023/B:JETT.0000009316.94309.66