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Scalable Delay Fault BIST for Use with Low-Cost ATE

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Abstract

We present a BIST architecture based on a Multi-Input Signature Register (MISR) expanding single input vectors into sequences, which are used for testing of delay faults. Input vectors can be stored on-chip or in the ATE; in the latter case, a low speed tester can be employed though the sequences are applied at-speed to the block-under-test. The number of input vectors (and thus the area demand on-chip or ATE memory requirements) can be traded for the test application time.

We propose several methods for generating input vectors, which differ in test application time, area requirements and algorithm run-time. As all of them require only a two-pattern test as input, IP cores can be handled by these methods.

The block-under-test can be switched off for some amount of time between application of consecutive input vectors. We provide arguments why this approach may be the only way to meet thermal and power constraints. Furthermore, we demonstrate how the BIST scheme can use these cool-down breaks for re-configuration.

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  1. Institute of Computer Science, Albert-Ludwigs-University, Georges-Köhler-Allee 51, 79110, Freiburg im Breisgau, Germany

    Ilia Polian & Bernd Becker

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  1. Ilia Polian
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Polian, I., Becker, B. Scalable Delay Fault BIST for Use with Low-Cost ATE. Journal of Electronic Testing 20, 181–197 (2004). https://doi.org/10.1023/B:JETT.0000023681.25483.59

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  • DOI: https://doi.org/10.1023/B:JETT.0000023681.25483.59

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