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Memory Fault Modeling Trends: A Case Study

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Abstract

In recent years, embedded memories are the fastest growing segment of system on chip. They therefore have a major impact on the overall Defect per Million (DPM). Further, the shrinking technologies and processes introduce new defects that cause previously unknown faults; such faults have to be understood and modeled in order to design appropriate test techniques that can reduce the DPM level. This paper discusses a new memory fault class, namely dynamic faults, based on industrial test results; it defines the concept of dynamic faults based on the fault primitive concept. It further shows the importance of dynamic faults for the new memory technologies and introduces a systematic way for modeling them. It concludes that current and future SRAM products need to consider testability for dynamic faults or leave substantial DPM on the table, and sets a direction for further research.

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Authors and Affiliations

  1. Faculty of Electrical Engineering, Mathematic and Computer Science, Computer Engineering Laboratory, Delft University of Technology, Mekelweg 4, 2628 CD, Delft, The Netherlands

    Said Hamdioui

  2. Intel Corporation, 2200 Mission College Boulevard, Santa Clara, CA, 95052, USA

    Said Hamdioui

  3. STMicroelectronics, 850 rue Jean Monnet, BP 16, F-38926, CROLLES Cedex, France

    Rob Wadsworth

  4. Intel Corporation, 2200 Mission College Boulevard, Santa Clara, CA, 95052, USA

    John Delos Reyes

  5. Faculty of Electrical Engineering, Mathematic and Computer Science, Computer Engineering Laboratory, Delft University of Technology, Mekelweg 4, 2628 CD, Delft, The Netherlands

    Ad J. van de Goor

Authors
  1. Said Hamdioui
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  2. Rob Wadsworth
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  3. John Delos Reyes
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  4. Ad J. van de Goor
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Hamdioui, S., Wadsworth, R., Reyes, J.D. et al. Memory Fault Modeling Trends: A Case Study. Journal of Electronic Testing 20, 245–255 (2004). https://doi.org/10.1023/B:JETT.0000029458.57095.bb

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  • DOI: https://doi.org/10.1023/B:JETT.0000029458.57095.bb

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