Abstract
This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell. Fault injection procedures and a fast fault simulation algorithm for transient faults were implemented around an event driven simulator. A statistical analysis was implemented to organize data sampled from simulations. The benchmarks show that the proposed algorithm is capable of injecting and simulating a large number of transient faults in complex designs. Also specific optimizations have been carried out, thus greatly reducing the simulation time compared to a sequential fault simulation approach.
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Alexandrescu, D., Anghel, L. & Nicolaidis, M. Simulating Single Event Transients in VDSM ICs for Ground Level Radiation. Journal of Electronic Testing 20, 413–421 (2004). https://doi.org/10.1023/B:JETT.0000039608.48856.33
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DOI: https://doi.org/10.1023/B:JETT.0000039608.48856.33