Abstract
Transient faults (TFs) are increasingly affecting microelectronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional electrical level simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a new model to estimate accurately the possible propagation of transient fault-due glitches through a CMOS combinational circuit. We will show how the proposed model can be applied in order to estimate the TF susceptibility of a circuit by simply considering the propagation delay of the datapath. Therefore, the proposed model is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to electrical level simulation. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations.
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Omaña, M., Rossi, D. & Metra, C. Model for Transient Fault Susceptibility of Combinational Circuits. Journal of Electronic Testing 20, 501–509 (2004). https://doi.org/10.1023/B:JETT.0000042514.37566.6d
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DOI: https://doi.org/10.1023/B:JETT.0000042514.37566.6d