Abstract
Fault tolerant design is a technique emerging in Integrated Circuits (ICs) to deal with the increasing error susceptibility (Soft Errors, Single Event Upsets, (SEUs)) caused by e.g. alpha particles. A side effect of these methods is that they also compensate for manufacturing defects, thereby increasing the yield and lowering the production cost in certain conditions. In this paper, it is shown that increasing the IC area (by applying fault tolerant design techniques for SEUs) leads to a synergistic advantage under certain conditions: lower production costs because of a better yield. To guide designers in deciding when the fault tolerant techniques are beneficial, break-even points between fault tolerant and regular designs are presented as function of IC area, fault tolerant overhead and defect density.
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References
M. Alderighi et al., “Achieving Fault Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs,” in Proc. IEEE Int. Symp. on Defects and Fault Tolerance in VLSI Systems, Fujiyoshida-city, Japan, Oct. 2000.
Y.-Y. Chen and S.J. Upadhyaya, “Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy,” IEEE Transaction on Computers, vol. 42, no. 9, Sept. 1993.
E. Dupont, M. Nicolaidis, and P. Rohr, “Embedded Robustness IPs for Transient-Error-Free IC's,” IEEE Design & Test of Computers, May–June 2002.
J.L. Hennesy and D.A. Patterson, Computer Architecture, a Quantitative Approach, chap. 1, 2nd edition, 1996.
N.K. Jha and J.A. Abraham, “Totally Self-Checking MOS Circuits under Realistic Physical Failures,” in Proc. International Conference on Computer Design, Oct. 1984, pp. 665–670
R. Kleihorst and N. Benschop, “Fault Tolerant ICs by Area-Optimized Error Correcting Codes,” in Proceedings 7th IEEE Intenational On-Line Testing Workshop (IOLTW01), Giardini Naxos, Italy, July 9–11, 2001.
I. Koren and Z. Koren, “Defect Tolerance in VLSI Circuits: Techniques and Yield analysis,” Proceedings of the IEEE, Sept. 1998, vol. 86, no. 9, pp. 1819–1837.
G. Muurling, “Fault-Tolerance in IC Design Using Error-Correcting Codes,” M.Sc. Thesis, Delft University of Technology, July 2000.
G. Muurling, R. Kleihorst, N. Benschop, R. van der Vleuten, and J. Simonis, “Error Correction for Combinational Logic Circuits,” in Proc. 21th Symp. on Information Theory (Benelux), Wassenaar, the Netherlands, May 25–26, 2000, pp. 25–31.
M. Nicolaidis, “Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies,” in Proc. VLSI Test Symposium, 1999, pp. 86–94.
J. von Neumann, “Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components,” in Automata Studies, Princeton University Press, 1956.
A.K. Nieuwland and R.P. Kleihorst, “The Positive Effect on IC Yield of Embedded Fault Tolerance for SEUs,” in Proc. 9th IEEE On-Line Testing Symposium (IOLTS), Kos, Greece, July 2003, pp. 75–79.
D. Pradhan and J. Stiffler, “Error-Correcting Codes and Self-Checking Circuits,” IEEE Computer, pp. 27–36, March 1980.
L. Spainhower and T.A. Gregg, “IBM S/390 Parallel Enterprise Server G5Fault Tolerance: A Historical Perspective,” IBM. Journal of Res. Develop, vol. 43, nos. 5/6, Sept./Nov. 1999.
C. H. Stapper and R.J. Rosner, “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation,” IEEE Transactions on Semiconductor Manufacturing, vol. 8, no. 2, pp. 95–102, May 1995.
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Nieuwland, A.K., Kleihorst, R.P. IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors. Journal of Electronic Testing 20, 533–542 (2004). https://doi.org/10.1023/B:JETT.0000042517.30698.ad
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DOI: https://doi.org/10.1023/B:JETT.0000042517.30698.ad