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Multiple Addition and Prefix Sum on a Linear Array with a Reconfigurable Pipelined Bus System

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Abstract

We present several fast algorithms for multiple addition and prefix sum on the Linear Array with a Reconfigurable Pipelined Bus System (LARPBS), a recently proposed architecture based on optical buses. Our algorithm for adding N integers runs on an N log M-processor LARPBS in O(log* N) time, where log* N is the number of times logarithm has to be taken to reduce N below 1 and M is the largest integer in the input. Our addition algorithm improves the time complexity of several matrix multiplication algorithms proposed by Li, Pan and Zheng (IEEE Trans. Parallel and Distributed Systems, 9(8):705–720, 1998). We also present several fast algorithms for computing prefix sums of N integers on the LARPBS. For integers with bounded magnitude, our first algorithm for prefix sum computation runs in O(log log N) time using N processors and in O(1) time using N 1+ε processors, for \(\frac{1}{3}\) ≤ ε < 1. For integers with unbounded magnitude, the first algorithm for multiple addition runs in O(log log N log* N) time using N log M processors, when M is the largest integer in the input. Our second algorithm for multiple addition runs in O(log* N) time using N 1+ε log M processors, for \(\frac{1}{3}\) ≤ ε < 1. We also show suitable extensions of our algorithm for real numbers.

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  1. Amitava Datta
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Datta, A. Multiple Addition and Prefix Sum on a Linear Array with a Reconfigurable Pipelined Bus System. The Journal of Supercomputing 29, 303–317 (2004). https://doi.org/10.1023/B:SUPE.0000032783.66123.63

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  • DOI: https://doi.org/10.1023/B:SUPE.0000032783.66123.63

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